TPS54317
www.ti.com
.....................................................................................................................................
SLVS619B – NOVEMBER 2005 – REVISED SEPTEMBER 2009
1.6 MHz, 3-V TO 6-V INPUT, 3-A SYNCHRONOUS STEP-DOWN SWIFT™ CONVERTER
Check for Samples:
TPS54317
1
FEATURES
•
60-mΩ MOSFET Switches for High Efficiency
at 3-A Continuous Output Current
Adjustable Output Voltage Down to 0.9 V With
1% Accuracy
Switching Frequency: Adjustable From
280 kHz to 1600 kHz
Externally Compensated for Design Flexibility
Fast Transient Response
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
Spacing Saving 4mm x 5mm QFN Packaging
For SWIFT Documentation, Application Notes,
and Design Software, see the TI website at
www.ti.com/swift
2
DESCRIPTION
As members of the SWIFT™ family of dc/dc
regulators,
the
TPS54317
low-input-voltage
high-output-current
synchronous-buck
PWM
converter integrates all required active components.
Included on the substrate with the listed features are
a true, high performance, voltage error amplifier that
provides high performance under transient conditions;
an undervoltage-lockout circuit to prevent start-up
until the input voltage reaches 3 V; an internally and
externally set slow-start circuit to limit in-rush
currents; and a power good output useful for
processor/logic reset, fault signaling, and supply
sequencing.
The TPS54317 device is available in a thermally
enhanced 24-pin QFN (RHF) PowerPAD™ package,
which eliminates bulky heatsinks. TI provides
evaluation modules and the SWIFT designer software
tool to aid in achieving high-performance power
supply designs to meet aggressive equipment
development cycles.
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
Low-Voltage, High-Density Systems With
Power Distributed at 5 V or 3.3 V
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs, and
Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
•
Simplified Schematic
Input
VIN
EFFICIENCY
vs
LOAD CURRENT
Output
100
95
90
TPS54317
PH
PWRGD
SS/ENA
SYNC
RT
VBIAS
AGND
Efficiency − %
BOOT
PGND
VSENSE
COMP
85
80
75
70
65
60
55
50
0
0.5
1
1.5
2
2.5
3
3.5
I
O
- Output Current − A
T
A
= 25
o
C,
V
I
= 3.3 V,
V
O
= 1.8 V,
fs = 1.1 MHz
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
Copyright © 2005–2009, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS54317
SLVS619B – NOVEMBER 2005 – REVISED SEPTEMBER 2009
.....................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
T
J
–40°C to 125°C
(1)
(2)
OUTPUT VOLTAGE
Adjustable Down to 0.9 V
PACKAGE
QFN (RHF)
(1) (2)
PART NUMBER
TPS54317RHF
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at
www.ti.com.
The RHF package is available in two different tape and reel quantities. Add an R suffix to the device type (i.e. TPS54317RHFR) for a
3000 piece reel and add a T suffix (TPS54317RHFT) for a 250 piece reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
VIN, SS/ENA, SYNC
V
I
Input voltage range
RT
VSENSE
BOOT
VBIAS, PWRGD, COMP
V
O
Output voltage range
PH (steady state)
PH (transient < 20 ns)
I
O
Output current range
PH
COMP, VBIAS
PH
Sink current
Voltage differential
Continuous power dissipation
T
J
T
stg
(1)
Operating virtual junction temperature range
Storage temperature
COMP
SS/ENA, PWRGD
AGND to PGND
6
6
6
10
±0.3
See Power Dissipation Rating Table
–40 to 150
–65 to 150
°C
°C
–0.3 to 7
–0.3 to 6
–0.3 to 4
–0.3 to 17
–0.3 to 7
–0.6 to 10
–2 to 10
Internally Limited
mA
A
mA
mA
V
UNIT
V
V
V
V
V
V
V
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
V
I
T
J
Input voltage range
Operating junction temperature
3
–40
NOM
MAX
6
125
UNIT
V
°C
2
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TPS54317
Copyright © 2005–2009, Texas Instruments Incorporated
TPS54317
www.ti.com
.....................................................................................................................................
SLVS619B – NOVEMBER 2005 – REVISED SEPTEMBER 2009
PACKAGE DISSIPATION RATINGS
(1)
PACKAGE
24-Pin RHF with solder
(1)
(2)
(2)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
19.7°C/W
THERMAL IMPEDANCE
JUNCTION-TO-CASE
1.7°C/W
Maximum power dissipation may be limited by overcurrent protection.
Test board conditions:
(a) 3 inch x 3 inch, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground plane on the bottom of the PCB
(d) 2 oz. copper ground planes on the 2 internal layers
(e) 6 thermal vias (see the Recommended land pattern,
Figure 12
)
ELECTRICAL CHARACTERISTICS
T
J
= –40°C to 125°C, V
I
= 3 V to 6 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE, VIN
V
I
Input voltage range, VIN
f
s
= 350 kHz, SYNC = 0.8 V, RT open
Quiescent current
f
s
= 550 kHz, SYNC
≥
2.5 V, RT open,
phase pin open
Shutdown, SS/ENA = 0 V
UNDERVOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
Rising and falling edge deglitch,
UVLO
(1)
BIAS VOLTAGE
V
O
Output voltage, VBIAS
Output current, VBIAS
Accuracy
Line regulation
(1)
Load regulation
(1)
OSCILLATOR
Internally set free-running frequency
range
Externally set free-running frequency
range
High-level threshold voltage, SYNC
Low-level threshold voltage, SYNC
Pulse duration, SYNC
Ramp valley
(1)
(1)
(1)
(3)
(3)
(2)
TEST CONDITIONS
MIN
3
TYP
MAX
6
UNIT
V
6.2
8.4
1
2.95
2.7
0.14
2.8
0.16
2.5
9.6
12.8
1.4
3
mA
V
V
µs
I
(VBIAS)
= 0
2.7
2.8
2.9
100
V
µA
V
%/V
%/A
CUMULATIVE REFERENCE
V
ref
0.882
I
L
= 1.5 A, f
s
= 1.1 MHz, T
J
= 25°C
I
L
= 0 A to 3 A, f
s
= 1.1 MHz, T
J
= 25°C
SYNC
≤
0.8 V, RT open
SYNC
≥
2.5 V, RT open
RT = 100 kΩ (1% resistor to AGND)
RT = 43 kΩ (1% resistor to AGND)
280
440
460
995
2.5
0.8
50
330
0.75
1
150
90%
1600
0.891
0.04
0.09
350
550
500
1075
420
660
540
1155
0.900
REGULATION
kHz
kHz
V
V
ns
kHz
V
V
ns
Frequency range, SYNC
Ramp amplitude (peak-to-peak)
Minimum controllable on time
Maximum duty cycle
(1)
(2)
(3)
Specified by design
Static resistive loads only
Specified by the circuit used in
Figure 10
.
Copyright © 2005–2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s):
TPS54317
3
TPS54317
SLVS619B – NOVEMBER 2005 – REVISED SEPTEMBER 2009
.....................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
T
J
= –40°C to 125°C, V
I
= 3 V to 6 V (unless otherwise noted)
PARAMETER
ERROR AMPLIFIER
Error amplifier open loop voltage gain
Error amplifier unity gain bandwidth
Error amplifier common-mode input
voltage range
I
IB
V
O
Input bias current, VSENSE
Output voltage slew rate (symmetric),
COMP
PWM comparator propagation delay
time, PWM comparator input to PH pin
(excluding dead time)
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Voltage to regulate using the internal
V
ref
, SS/ENA
Enable hysteresis voltage, SS/ENA
Falling edge deglitch, SS/ENA
Internal slow-start time
Charge current, SS/ENA
Discharge current, SS/ENA
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage
(4)
(4)
(4)
(4)
TEST CONDITIONS
1 kΩ COMP to AGND
(4)
Parallel 10 kΩ, 160 pF COMP to AGND
Powered by internal LDO
(4)
VSENSE = V
ref
(4)
MIN
90
3
0
TYP
110
5
MAX
UNIT
dB
MHz
VBIAS
60
250
V
nA
V/µs
1
1.4
PWM COMPARATOR
10 mV overdrive
(4)
70
85
ns
0.82
1.2
1.95
0.03
2.5
1.4
2.2
V
V
V
µs
2.6
SS/ENA = 0 V
SS/ENA = 0.2 V, V
I
= 2.7 V
VSENSE falling
3
1.5
3.35
5
2.3
90
3
35
4.1
8
4
ms
µA
mA
%V
ref
%V
ref
µs
Power good falling edge deglitch
Leakage current, PWRGD
CURRENT LIMIT
Current limit trip point
Output saturation voltage, PWRGD
I
(sink)
= 2.5 mA
V
I
= 5.5 V
V
I
= 3 V, output shorted
V
I
= 6 V, output shorted
(4)
(4)
0.18
0.3
1
V
µA
4
4.5
6.5
7.5
100
200
A
ns
ns
165
°C
°C
88
136
mΩ
Current limit leading edge blanking
time
(4)
Current limit total response time
THERMAL SHUTDOWN
Thermal shutdown trip point
OUTPUT POWER MOSFETS
r
DS(on)
(4)
Power MOSFET switches
V
I
= 6 V
V
I
= 3 V
(4)
(4)
(4)
135
150
10
59
85
Thermal shutdown hysteresis
Specified by design
4
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Product Folder Link(s):
TPS54317
Copyright © 2005–2009, Texas Instruments Incorporated
TPS54317
www.ti.com
.....................................................................................................................................
SLVS619B – NOVEMBER 2005 – REVISED SEPTEMBER 2009
PIN ASSIGNMENTS
RHF PACKAGE
(BOTTOM VIEW)
PWRGD
COMP
BOOT
PH
PH
PH
6
1
2
3
4
5
PH
7
8
9
10
11
12
VSNS
AGND
RT
NC
SYNC
24
23
22
21
20
19
18
17
16
15
14
13
PH
PH
NC
PGND
PGND
Exposed
Thermal Pad
(Pin 25)
VIN
VIN
VIN
PGND
TERMINAL FUNCTIONS
TERMINAL
NAME
COMP
PWRGD
BOOT
PH
PGND
VIN
VBIAS
SS/ENA
SYNC
RT
AGND
VSNS
NC
NO.
1
2
3
4-9
11-14
15-17
18
19
20
22
23, 25
24
10, 21
DESCRIPTION
Error amplifier output. Connect compensation network from COMP to VSENSE.
Power good open drain output. High when VSENSE
≥
90% V
ref
, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
Bootstrap input. 0.022-μF to 0.1-μF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low ESR 1-μF to 10-μF ceramic capacitor.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low ESR 0.1-μF to 1.0-μF ceramic capacitor.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f
s
.
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
and SYNC pin. Make PowerPAD connection to AGND.
Error amplifier inverting input.
Not connected internally.
SS/ENA
VBIAS
PGND
Copyright © 2005–2009, Texas Instruments Incorporated
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Product Folder Link(s):
TPS54317
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