ADVANCE INFORMATION
Am29LV160M
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) MirrorBit
TM
3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Low power consumption (typical values at 5 MHz)
—
—
—
—
400 nA standby mode current
15 mA read current
40 mA program/erase current
400 nA Automatic Sleep mode current
■
Single power supply operation
— 3 V for read, erase, and program operations
■
Manufactured on 0.23 µm MirrorBit
TM
process
technology
— Fully compatible with Am29LV160D device
■
Package options
— 48-ball Fine-pitch BGA
— 64-ball Fortified BGA
— 48-pin TSOP
SOFTWARE & HARDWARE FEATURES
■
SecSi (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
■
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-
one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
■
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
■
Top or bottom boot block configurations available
■
Minimum 100,000 erase cycle guarantee per sector
■
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■
Hardware features
— Sector Protection: hardware-level method of
preventing write operations within a sector
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
■
High performance
— Access times as fast as 70 ns
— 0.4 s typical sector erase time
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
25974
Rev:
A
Amendment/+3
Issue Date:
January 6, 2003
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV160M is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes or 1,048,576
words. The device is offered in a 48-ball Fine-pitch
BGA, 64-ball Fortified BGA, and 48-pin TSOP pack-
ages. The word-wide data (x16) appears on DQ15–
DQ0; the byte-wide (x8) data appears on DQ7–DQ0.
This device is . The device requires only a
single 3.0
volt power supply
for both read and write functions,
designed to be programmed in-system with the stan-
dard system 3.0 volt V
CC
supply. The device can also
be programmed in standard EPROM programmers.
The device offers access times of 70, 90, and 120 ns,
allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or
monitor the
Ready/Busy# (RY/BY#)
output to deter-
mine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The
Program
Suspend/Program Resume
feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power c ons umption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The
SecSi (Secured Silicon) Sector
provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
2
Am29LV160M
January 6, 2003
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29LV160M Device Bus Operations ..............................10
Command Definitions ............................................................. 27
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling ................................................................. 29
Figure 7. Data# Polling Algorithm .................................................. 29
RY/BY#: Ready/Busy# ............................................................ 30
DQ6: Toggle Bit I .................................................................... 30
DQ2: Toggle Bit II ................................................................... 30
Reading Toggle Bits DQ6/DQ2 ............................................... 30
Figure 8. Toggle Bit Algorithm........................................................ 31
Word/Byte Configuration ........................................................ 10
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 11
Program and Erase Operation Status .................................... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 2. Sector Address Tables (Am29LV160MT) .........................13
Table 3. Sector Address Tables (Am29LV160MB) .........................14
DQ5: Exceeded Timing Limits ................................................ 32
DQ3: Sector Erase Timer ....................................................... 32
Table 12. Write Operation Status ................................................... 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 9. Maximum Negative Overshoot Waveform ...................... 33
Figure 10. Maximum Positive Overshoot Waveform...................... 33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Test Setup..................................................................... 35
Table 13. Test Specifications ......................................................... 35
Figure 12. Input Waveforms and Measurement Levels ................. 35
Autoselect Mode ..................................................................... 15
Table 4. Am29LV160M Autoselect Codes (High Voltage Method) .15
Sector Protection/Unprotection ............................................... 15
Temporary Sector Unprotect .................................................. 15
Figure 1. Temporary Sector Unprotect Operation........................... 16
Figure 2. In-System Single High Voltage Sector Protect/Unprotect Al-
gorithms .......................................................................................... 17
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Read Operations .................................................................... 36
Figure 13. Read Operations Timings ............................................. 36
Hardware Reset (RESET#) .................................................... 37
Figure 14. RESET# Timings .......................................................... 37
SecSi (Secured Silicon) Sector Flash Memory Region .......... 18
Table 5. SecSi Sector Addressing ..................................................18
Figure 3. SecSi Sector Protect Verify.............................................. 19
Word/Byte Configuration (BYTE#) ........................................ 38
Figure 15. BYTE# Timings for Read Operations............................ 38
Figure 16. BYTE# Timings for Write Operations............................ 38
Common Flash Memory Interface (CFI) ................................. 19
Table 6. CFI Query Identification String ..........................................19
Table 7. System Interface String .....................................................20
Table 8. Device Geometry Definition ..............................................20
Table 9. Primary Vendor-Specific Extended Query ........................21
Erase/Program Operations ..................................................... 39
Figure 17. Program Operation Timings..........................................
Figure 18. Chip/Sector Erase Operation Timings ..........................
Figure 19. Data# Polling Timings (During Embedded Algorithms).
Figure 20. Toggle Bit Timings (During Embedded Algorithms)......
Figure 21. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ............................................................
Figure 22. Temporary Sector Unprotect/Timing Diagram ..............
Figure 23. Sector Protect/Unprotect Timing Diagram ....................
Figure 24. Alternate CE# Controlled Write Operation Timings ......
40
41
42
42
43
43
44
46
Hardware Data Protection ...................................................... 21
Low V
CC
Write Inhibit .............................................................. 21
Write Pulse “Glitch” Protection ............................................... 21
Logical Inhibit .......................................................................... 21
Power-Up Write Inhibit ............................................................ 21
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 22
Reading Array Data ................................................................ 22
Reset Command ..................................................................... 22
Autoselect Command Sequence ............................................ 22
Word/Byte Program Command Sequence ............................. 22
Unlock Bypass Command Sequence ..................................... 23
Figure 4. Program Operation .......................................................... 23
Chip Erase Command Sequence ........................................... 23
Sector Erase Command Sequence ........................................ 24
Erase Suspend/Erase Resume Commands ........................... 24
Figure 5. Erase Operation............................................................... 25
Program Suspend/Program Resume Command Sequence ... 26
Figure 6. Program Suspend/Program Resume............................... 26
Erase and Programming Performance . . . . . . . 47
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 47
TSOP Pin and BGA Package Capacitance . . . . . 47
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48
TS 048—48-Pin Standard TSOP ............................................ 48
TSR048—48-Pin Reverse TSOP ........................................... 49
FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA)
6 x 8 mm Package .................................................................. 50
LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm
Package .................................................................................. 51
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
January 6, 2003
Am29LV160M
3
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Regulated Voltage Range: V
CC
= 3.0–3.6 V
Full Voltage Range: V
CC
= 2.7–3.6 V
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note:
See
“AC Characteristics”
for full specifications.
70R
70
70
70
30
Am29LV160M
90R
90
90
90
35
120R
120
120
120
50
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
RESET#
Erase Voltage
Generator
Input/Output
Buffers
Sector Switches
DQ15–DQ0 (A-1)
WE#
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A19–A0
4
Am29LV160M
January 6, 2003
A D V A N C E
I N F O R M A T I O N
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
January 6, 2003
Am29LV160M
5
Microcontroller MCU
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