SY87813L
3.3V, 28Mbps to 1.3Gbps AnyRate
Clock and Data Recovery
®
General Description
The SY87813L is a complete clock recovery and data
retiming integrated circuit for data rates from 28Mbps up
to 1.3Gbps NRZ. The device is ideally suited for
SONET/SDH/ATM and Fibre Channel applications and
other high-speed data transmission systems.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming
data stream. The VCO center frequency is controlled by
the reference clock frequency and the selected divide
ratio. On-chip clock generation is performed through the
use of a frequency multiplier PLL with a byte rate source
as reference.
The SY87813L also includes a link fault detection circuit.
Datasheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
AnyRate
®
Features
•
3.3V power supply
•
SONET/SDH/ATM compatible
•
Clock and data recovery from 28Mbps up to 1.3Gbps
NRZ data stream; clock generation from 28MHz to
1.3GHz
•
Two on-chip PLLs: one for clock generation and
another for clock recovery
•
Selectable reference frequencies
•
Differential PECL high-speed serial I/O
•
Line receiver input: no external buffering needed
•
Link fault indication
•
100K ECL-compatible I/O
•
Industrial temperature range (–40°C to +85°C)
•
Available in 32-pin EPAD-TQFP
Applications
•
•
•
•
•
SONET/SDH/ATM OC-1 and OC-3, OC-12, OC-24
Fibre Channel, ESCON, SMPTE 259
Gigabit Ethernet/Fast Ethernet
Proprietary architecture up to 1.3Gbps
CEPT E-3/E-4/E-5
Markets
•
Telecom/Datacom
•
Fiber optics
•
Storage networks
AnyRate is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
November 2006
M9999-112806-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY87813L
Ordering Information
(1)
Part Number
SY87813LHG
SY87813LHGTR
(2)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
Package
Type
H32-1
H32-1
Operating
Range
Industrial
Industrial
Package
Marking
SY87813LHG with
Pb-Free bar-line indicator
SY87813LHG with
Pb-Free bar-line indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
32-Pin EPAD-TQFP (H32-1)
November 2006
2
M9999-112806-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY87813L
Pin Description
Pin Number
1
2
3
Pin Name
REFCLKSEL
RDINP,
RDINN
Pin Name
REFCLK Select (TTL Input). This input selects the single-ended TTL REFCLK input or the
differential PECL REFCLKP/REFCLKN inputs. REFCLKSEL = HIGH selects PECL inputs.
Serial Data Input. Differential PECL: These built-in line receiver inputs are connected to the
differential receive serial data stream. An internal receive PLL recovers the embedded clock
(RCLK) and data (RDOUT) information. The incoming data rate can be within one of eight
frequency ranges depending upon the state of the FREQSEL pins. See “Frequency
Selection” Table.
Frequency Select. TTL Inputs: These inputs select the output clock frequency range as
shown in the “Frequency Selection” Table.
Reference Clock. (Input): These inputs are used as the reference for the internal frequency
synthesizer and the “training” frequency for the receiver PLL to keep it centered in the
absence of data coming in on the RDIN inputs. REFCLK is single-ended TTL and REFCLKP
and REFCLKN are differential PECL inputs selected by the REFCLKSEL pin
Carrier Detect. PECL Input: This input controls the recovery function of the Receive PLL and
can be driven by the carrier detect output of optical modules or from external transition
detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be
internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault
Indicator output LFIN forced LOW and the clock recovery PLL forced to lock onto the clock
frequency generated from REFCLK.
No connect.
Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.
Analog Ground.
Ground. Ground pin and exposed pad must be connected to the same ground plane.
Clock Recovery PLL Loop Filter. External loop filter pins for the receiver PLL.
Clock Select. TTL Input: This input is used to select either the recovered clock of the receiver
PLL (TCLKSEL = HIGH) or the clock of the frequency synthesizer (TCLKSEL = LOW) to the
TCLK outputs.
Clock Output (Differential PECL): The PECL 100k outputs represent either the recovered
clock (TCLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock
of the frequency synthesizer (TCLKSEL = LOW). These outputs must be terminated with 50Ω
to V
CC
-2V or equivalent. This applies even if these outputs are not used.
Output Supply Voltage. Bypass with 0.1µF//0.01µF low ESR capacitors as close to V
CC
pins
as possible.
(1)
Clock Output (Differential PECL): These PECL 100k outputs represent the recovered clock
used to sample the recovered data (RDOUT).
Receive Data Output (Differential PECL): These PECL 100k outputs represent the recovered
data from the input data stream (RDIN). This recovered data is specified against the rising
edge of RCLK. These outputs must be terminated with 50Ω to V
CC
-2V or equivalent. This
applies even if these outputs are not used.
Divider Select. TTL Inputs: These inputs select the ratio between the output clock frequency
(RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency
Selection” Table.
4
6
7
5
28
29
26
FREQSEL1
FREQSEL2
FREQSEL3
REFCLK,
REFCLKP,
REFCLKN
CD
8
9
10
11
12, 13
15
14
16
NC
PLLSP
PLLSN
GNDA
GND
PLLRP
PLLRN
TCLKSEL
18
17
TCLKP,
TCLKN
19, 22
21
20
24
23
VCCO
RCLKP,
RCLKN
RDOUTP
RDOUTN
32
25
Note:
DIVSEL1
DIVSEL2
1. VCC, VCCA, VCCO must be the same value.
November 2006
3
M9999-112806-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY87813L
Pin Description
(continued)
Pin Number
27
30
31
Pin Name
VCC
VCCA
LFIN
Pin Name
Supply Voltage. Bypass with 0.1µF//0.01µF low ESR capacitors as close to V
CC
pins as
possible.
(1)
Analog Supply Voltage. Bypass with 0.1µF//0.01µF low ESR capacitors as close to V
CC
pins
as possible.
(1)
Link Fault Indicator (TTL Output): This output indicates the status of the input data stream
RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto
the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency
range of the Receive PLL (900ppm).
Note:
1. VCC, VCCA, VCCO must be the same value.
November 2006
4
M9999-112806-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY87813L
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ................................... -0.5V to +4.0V
Input Voltage (V
IN
) ........................................... -0.5V to V
CC
Output Current (I
OUT
)
Continuous........................................................ ±50mA
Surge .............................................................. ±100mA
Lead Temperature (soldering, 20sec.) ................... +260°C
Storage Temperature (T
s
) ........................-65°C to +150°C
Operating Ratings
(2)
Input Voltage (V
CC
)............................ +3.15V to +3.45V
Ambient Temperature (T
A
) ................... –40°C to +85°C
Junction Thermal Resistance
(3)
EPAD-TQFP (θ
JA
)
0lfpm airflow........................................ 27.6°C/W
200lfpm airflow.................................... 22.6°C/W
500lfpm airflow.................................... 20.7°C/W
DC Electrical Characteristics
Symbol
V
CC
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Condition
Min
3.15
Typ
3.3
120
Max
3.45
165
Units
V
mA
PECL 100K DC Electrical Characteristics
(4)
V
CC
= V
CCO
= V
CCA
= 3.3V ±5%; R
L
= 50Ω to V
CC
-2V; T
A
= –40°C to +85°C, unless otherwise noted.
Symbol
V
IH
V
IL
V
OH
V
OL
V
OSW
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing
Input LOW Current
V
IN
= V
IL
(Min)
Condition
Min
V
CC
-1.165
V
CC
-1.810
V
CC
-1.085
V
CC
-1.830
600
0.5
750
Typ
Max
V
CC
-0.880
V
CC
-1.475
V
CC
-0.880
V
CC
-1.620
900
Units
V
V
V
V
mV
µA
TTL DC Electrical Characteristics
(4)
V
CC
= V
CCO
= V
CCA
= 3.3V ±5%; T
A
= –40°C to +85°C, unless otherwise noted.
Symbol
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OS
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Using JEDEC standard test boards with die attach pad soldered to PCB. See www.amkor.com for additional package details.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input LOW Current
Output Short-Circuit Current
Condition
Min
2.0
Typ
Max
V
CC
0.8
Units
V
V
V
V
µA
µA
µA
mA
I
OH
= -0.4mA
I
OL
= 4mA
V
IN
= 2.7V, V
CC
= Max.
V
IN
= V
CC
, V
CC
= Max.
V
IN
= 0.5V, V
CC
= Max.
V
OUT
= 0V, (Max., 1 sec.)
2.0
0.5
-175
+100
-300
-15
-100
November 2006
5
M9999-112806-B
hbwhelp@micrel.com
or (408) 955-1690
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