CD40105BMS
December 1992
CMOS FIFO Register
Description
CD40105BMS is a low-power first-in-first-out (FIFO) “elastic”
storage register that can store 16 4-bit words. It is capable of
handling input and output data at different shifting rates. This
feature makes it particularly useful as a buffer between asyn-
chronous systems.
Each word position in the register is clocked by a control flip-
flop, which stores a marker bit. A “1” signifies that the posi-
tion’s data is filled and a “0” denotes a vacancy in that posi-
tion. The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the succeeding
flip-flop. When a control flip-flop is in the “0” state and sees a
“1” in the preceding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding flip-flop to
“0”. The first and last control flip-flops have buffered outputs.
Since all empty locations “bubble” automatically to the input
end, and all valid data ripple through to the output end, the
status of the first control flip-flop (DATA-IN READY) indicates
if the FIFO is full, and the status of the last flip-flop (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
Loading Data
- Data can be entered whenever the DATA-IN
READY (DIR) flag is high, by a low to high transition on the
SHIFT-IN (SI) input. This input must go low momentarily
before the next word is accepted by the FIFO. The DIR flag
will go low momentarily, until that data have been transferred
to the second location. The flag will remain low when all 16-
word locations are filled with valid data, and further pulses
on the SI input will be ignored until DIR goes high.
Continued on next page
Features
• 4 Bits x 16 Words
• High Voltage Type (20V Rating)
• Independent Asynchronous Inputs and Outputs
• 3-State Outputs
• Expandable in Either Direction
• Status Indicators on Input and Output
• Reset Capability
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Bit Rate Smoothing
• CPU/Terminal Buffering
• Data Communications
• Peripheral Buffering
• Line Printer Input Buffers
• Auto Dialers
• CRT Buffer Memories
• Radar Data Acquisition
Pinout
3 - STATE
CONTROL 1
DIR
SI
D0
D1
D2
D3
VSS
2
3
4
5
6
7
8
CD40105BMS
TOP VIEW
16 VDD
15 SO
14 DOR
13 Q0
12 Q1
11 Q2
10 Q3
9 MR
Functional Diagram
3-STATE
CONTROL
D0
D1
D2
D3
SHIFT IN
SHIFT OUT
4
5
6
7
3
15
9
1
13
12
11
10
14
2
Q0
Q1
Q2
Q3
DATA-OUT
READY
DATA-IN
READY
MASTER
RESET
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3353
7-1317
CD40105BMS
Unloading Data
- As soon as the first word has rippled to
the output, DATA-OUT READY (DOR) goes high, and data
can be removed by a falling edge on the SO input. This fall-
ing edge causes the DOR signal to go low while the word on
the output is dumped and the next word moves to the output.
As long as valid data are available in the FIFO, the DOR sig-
nal will go high again signifying that the next word is ready at
the output. When the FIFO is empty, DOR will remain low,
and any further commands will be ignored until a “1” marker
ripples down to the last control register, when DOR goes
high. Unloading of data is inhibited while the 3-state control
input is high. The 3-state control signal should not be shifted
from high to low (data outputs turned on) while the SHIFT-
OUT is at logic 0. This level change would cause the first
word to be shifted out (unloaded) immediately and the data
to be lost.
Cascading
- The CD40105BMS can be cascaded to form
longer registers simply by connecting the DIR to SO and
DOR to SI. In the cascaded mode, a MASTER RESET pulse
must be applied after the supply voltage is turned on. For
words wider than 4 bits, the DIR and the DOR outputs must
be gated together with AND gates. Their outputs drive the SI
and SO inputs in parallel, if expanding is done in both direc-
tions (see Figures 9 and 11).
3-State Outputs
- In order to facilitate data busing, 3-state
outputs are provided on the data output lines, while the load
condition of the register can be detected by the state of the
DOR output.
Master Reset
- A high on the MASTER RESET (MR) sets all
the control logic marker bits to “0”. DOR goes low and DIR
goes high. The contents of the data register are not
changed, only declared invalid, and will be superseded when
the first word is loaded. The shift-in must be low during Mas-
ter Reset.
The CD40105BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
Logic Diagram
MASTER
RESET
2
DATA IN READY
(DIR)
SHIFT
OUT
*
15
1
*
3 - STATE
CONTROL
(OUTPUT
ENABLE)
*
9
SHIFT
IN
*
3
POSITIONS
DATA
READY
14
(DOR)
R
16
S
Q
Q
R
S
Q
R
S
Q
R
1
S
Q
Q
R
2
S
Q
Q
4 - 15
*
D0
*
D1
*
D2
*
D3
4
CL
5
6
7
POS 1
POS 2
VDD
POS 3
POS 16
CL
CL
CL
CL
CL
CL
CL
CL
4
LATCHES
4
LATCHES
4
LATCHES
4
LATCHES
3
STATE
OUTPUT
BUFFERS
13 Q0
12 Q1
11 Q2
10 Q3
*
ALL INPUTS PROTECTED BY
COS/MOS PROTECTION
NETWORK
DETAIL OF LATCHES
p
n
CL
CL
p
n
VSS
CL
7-1318
Specifications CD40105BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θ
ja
θ
jc
o
C/W
o
C/W
Ceramic DIP and FRIT Package . . . . . 80
20
Flatpack Package . . . . . . . . . . . . . . . . 70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For T
A
= -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For T
A
= +100
o
C to +125
o
C (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For T
A
= Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
(Note 4)
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low (Note
2)
Input Voltage High
(Note 2)
Tri-State Output
Leakage
VIL
VIH
VIL
VIH
IOZL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 15V, VOH > 13.5V, VOL < 1.5V
VDD = 15V, VOH > 13.5V, VOL < 1.5V
VIN = VDD or GND
VOUT = 0V
VDD = 20V
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2
VDD = 18V
3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
MIN
-
-
-
-100
-1000
-100
-
-
-
-
MAX
10
1000
10
-
-
-
100
1000
100
50
-
-
-
-
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
UNITS
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
+25
o
C, +125
o
C, -55
o
C 14.95
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C
+125
o
C
-55
o
C
-
3.5
-
11
-0.4
-12
-0.4
0.53
1.4
3.5
-
-
-
-
-2.8
0.7
VOH > VOL <
VDD/2 VDD/2
1.5
-
4
-
-
-
-
V
V
V
V
µA
µA
µA
7-1319
Specifications CD40105BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
MIN
-
-
-
MAX
0.4
12
0.4
UNITS
µA
µA
µA
PARAMETER
Tri-State Output
Leakage
SYMBOL
IOZH
CONDITIONS
(NOTE 1)
VIN = VDD or GND
VOUT = VDD
VDD = 20V
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
4. VDD = 2.8V/3.0V, RL = 100K to VDD
VDD = 20V/18V, RL = 10K to VDD
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
LIMITS
MIN
-
-
-
-
-
-
-
-
-
-
1.5
1.11
MAX
370
500
320
432
4
5.4
280
378
200
270
-
-
UNITS
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
MHz
MHz
PARAMETER
Propagation Delay
Shift Out or Reset to
Data-Out Ready
Propagation Delay
Shift In to Data-In Ready
Propagation Delay
Ripple through Delay In-
put to Output
Propagation Delay
3-State Control to Data
Out
Transition Time
SYMBOL
TPHL1
CONDITIONS
(NOTE 1)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V, VIN = VDD or GND
(Note 2, 3)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V (Note 1, 2),
VIN = VDD or GND
TPHL2
TPLH3
TPZH
TTHL
TTLH
FCL
Maximum Shift-In or
Shift-Out Rate
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
1, 2
TEMPERATURE
-55
o
C, +25
o
C
+125
o
C
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
Output Voltage
Output Voltage
Output Voltage
Output Voltage
VOL
VOL
VOH
VOH
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
1, 2
1, 2
1, 2
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
MIN
-
-
-
-
-
-
-
-
4.95
9.95
MAX
5
150
10
300
10
600
50
50
-
-
UNITS
µA
µA
µA
µA
µA
µA
mV
mV
V
V
7-1320
Specifications CD40105BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Output Current (Sink)
SYMBOL
IOL5
CONDITIONS
VDD = 5V, VOUT = 0.4V
NOTES
1, 2
TEMPERATURE
+125
o
C
-55
o
C
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
-55
o
C
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-55
o
C
Input Voltage Low
Input Voltage High
Propagation Delay
Shift or Reset to Data Out
Ready
Propagation Delay Ripple
through Delay Input to
Output
Propagation Delay
Shift-In to Data-In Ready
Propagation Delay
Shift Out to QN Out
VIL
VIH
TPHL1
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V
VDD = 15V
TPLH3
VDD = 10V
VDD = 15V
TPHL2
VDD = 10V
VDD = 15V
TPHL4
TPLH4
VDD = 5V
VDD = 10V
VDD = 15V
Propagation Delay
3-State Control to Data
Out
Propagation Delay
3-State Control to Data
Out
Maximum Shift-In or
Shift-Out Rate
Maximum Shift-In or
Shift-Out Rise Time
TPZH
TPZL
TTHZ
TPLZ
FCL
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TR
VDD = 5V
VDD = 10V
VDD = 15V
Maximum Shift-In Fall
Time
TF
VDD = 5V
VDD = 10V
VDD = 15V
Maximum Shift-Out Fall
Time
TF
VDD = 5V
VDD = 10V
VDD = 15V
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 4
1, 2, 3
1, 2, 3
1, 2
1, 2
3
3
3
3
3
3
3
3
3
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
7
-
-
-
-
-
-
-
-
-
-
-
-
-
3
4
-
-
-
-
-
-
-
-
-
-
180
130
2
1.4
130
90
420
380
250
120
80
100
80
-
-
15
15
15
15
15
15
15
5
5
V
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
MIN
0.36
0.64
0.9
1.6
2.4
4.2
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
7-1321
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