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5T9050PGGI

Description
TSSOP-28, Tube
Categorylogic    logic   
File Size338KB,10 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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5T9050PGGI Overview

TSSOP-28, Tube

5T9050PGGI Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP28,.25
Contacts28
Manufacturer packaging codePGG28
Reach Compliance Codecompliant
ECCN codeEAR99
series5T
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G28
JESD-609 codee3
length9.7 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
MaximumI(ol)0.012 A
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals28
Actual output times5
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP28,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply2.5 V
Prop。Delay @ Nom-Sup1.8 ns
propagation delay (tpd)1.8 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.025 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
minfmax200 MHz
Base Number Matches1
2.5V Single Data Rate 1:5 Clock Buffer
Terabuffer™ Jr.
5T9050
DATA SHEET
FEATURES:
DESCRIPTION:
Optimized for 2.5V LVTTL
Guaranteed Low Skew < 25ps (max)
Very low duty cycle distortion < 300 (max)
High speed propagation delay < 1.8ns. (max)
Up to 200MHz operation
Very low CMOS power levels
Hot insertable and over-voltage tolerant inputs
1:5 fanout buffer
2.5V V
DD
Available in TSSOP package
For New Designs use functional replacement 8L30110
The 5T9050 2.5V single data rate (SDR) clock buffer is a single-ended input
to five single-ended outputs buffer built on advanced metal CMOS technology.
The SDR clock buffer fanout from a single input to five single-ended outputs
reduces the loading on the preceding driver and provides an efficient clock
distribution network. Multiple power and grounds reduce noise.
APPLICATIONS:
• Clock and signal distribution
FUNCTIONAL BLOCK DIAGRAM
5T9050 REVISION A 11/2/15
1
©2015 Integrated Device Technology, Inc.

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