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870919BRILF

Description
QSOP-28, Tube
Categorylogic    logic   
File Size395KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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870919BRILF Overview

QSOP-28, Tube

870919BRILF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQSOP
package instructionQSOP-28
Contacts28
Manufacturer packaging codePCG28
Reach Compliance Codecompliant
ECCN codeEAR99
series870919
Input adjustmentMUX
JESD-30 codeR-PDSO-G28
JESD-609 codee3
length9.9 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs1
Number of terminals28
Actual output times7
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Same Edge Skew-Max(tskwd)0.5 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
minfmax160 MHz
Base Number Matches1
LVCMOS Clock Generator
ICS870919I
DATA SHEET
General Description
The ICS870919I is an LVCMOS clock generator that uses an internal
phase lock loop (PLL) for frequency multiplication and to lock the
low-skew outputs to the selected reference clock. The device offers
eight outputs. The PLL loop filter is completely internal and does not
require external components. Several output configurations of the
PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow
applications to optimize frequency generation over a wide range of
input reference frequencies. The PLL can also be disabled by the
PLL_EN control signal to allow for low frequency or DC testing. The
LOCK output asserts to indicate when phase-lock has been
achieved. The ICS870919I device is a member of the family of high
performance clock solutions from IDT.
Features
Two selectable single-ended input reference clocks
Eight single-ended clock outputs
Internal PLL does not require external loop filter components
5V tolerant inputs
Maximum output frequency: 160MHz, (2XQ output)
Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs)
LVCMOS interface levels for all inputs and outputs
PLL disable feature for low-frequency testing
PLL lock output
Selectable synchronization of output to input edge
Output drive capability: ±24mA
Output skew: 300ps (maximum), Q0:Q4
Output skew: 500ps (maximum), all outputs
Full 3.3V supply voltage
Available in lead-free (RoHS 6) packages
-40°C to 85°C ambient operating temperature
Block Diagram
LOCK
0
1
÷2
0
÷1
÷2
2XQ
Q0
Q1
Q2
SYNC0
SYNC1
REF_SEL
0
1
f
REF
PLL
f
VCO
20MHz - 160MHz
1
FEEDBACK
nPE
PLL_EN
FREQ_SEL
÷4
Q3
Q4
nQ5
Q/2
OE/nRST
ICS870919BVI REVISION B JANUARY 10, 2012
1
©2012Integrated Device Technology, Inc.
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