Silicon Delay Line, 1-Func, 4-Tap, True Output, CMOS, PDIP14,
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | DALLAS |
| Reach Compliance Code | unknown |
| Is Samacsys | N |
| Other features | 'DELAY FROM INPUT TO 4 TAPS[NS] = 6,10.5,10.7,15.2; TAP TO TAP DELAY TOL. [NS] VARIES' |
| series | CMOS/TTL |
| Input frequency maximum value (fmax) | 71.43 MHz |
| JESD-30 code | R-PDIP-T14 |
| JESD-609 code | e0 |
| Logic integrated circuit type | SILICON DELAY LINE |
| Number of functions | 1 |
| Number of taps/steps | 4 |
| Number of terminals | 14 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| Output polarity | TRUE |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP14,.3 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5 V |
| Maximum supply current (ICC) | 110 mA |
| programmable delay line | NO |
| Prop。Delay @ Nom-Sup | 15 ns |
| Certification status | Not Qualified |
| Maximum supply voltage (Vsup) | 5.25 V |
| Minimum supply voltage (Vsup) | 4.75 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| Total delay nominal (td) | 15.2 ns |
| Base Number Matches | 1 |
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