Static Discharge Voltage ........................................... >2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
[3]
Parameter
V
DD
T
A
C
L
f
REF
f
REF
Supply Voltage
Operating Temperature, Ambient
Max. Load Capacitance per output
External Reference Crystal
External Reference Clock
[4, 5]
10.0
1.0
Description
Min.
4.5 (3.0)
0
Max.
5.5 (3.6)
70
25 (15)
25.0
30.0
Unit
V
°C
pF
MHz
MHz
Electrical Characteristics
V
DD
= 5V (3.3V)
±10%,
T
A
= 0°C to +70°C
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
Description
HIGH-Level Output Voltage
LOW-Level Output Voltage
HIGH-Level Input Voltage
[6]
LOW-Level Output Voltage
[6]
Input HIGH Current
Input LOW Current
Output Leakage Current
V
DD
Supply Current
[7]
V
DD
Power Supply Current in
Power-down Mode
I
OL
= 4.0 mA
Except Crystal Pins
Except Crystal Pins
V
IN
= V
DD
– 0.5V
V
IN
= 0.5V
Three State Outputs
V
DD
= V
DD
max. 5V (3.3V) operation, C
L
= 25 pF (15 pF)
Power-down Active, 5V Operation
40 (24)
100
<100
<100
2.0
0.8
150
150
250
60 (40)
200
Conditions
I
OH
= –4.0 mA
Min.
2.4
0.4
Typ.
Max.
Unit
V
V
V
V
µA
µA
µA
mA
µA
Notes:
1. For best accuracy, use a parallel-resonant crystal, C
L
=17 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal).
3. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses.
4. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
5. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
6. Xtal inputs have CMOS thresholds.
7. Load = max, typical configuration, f
REF
= 14.318 MHz. Specific configurations may vary.
Document #: 38-07136 Rev. **
Page 2 of 6
CY2081
Switching Characteristics
[8]
Parameter
t
1
t
1
t
1A
t
1B
t
1C
t
1D
Name
Output Period
Output Period
Clock Jitter
[9]
Clock Jitter
[9]
Clock Jitter
[9]
Clock Jitter
[9]
Output Duty Cycle
[10]
Description
Clock output range, 5V operation
Clock output range, 3.3V operation
Peak-to-peak period jitter,% of clock period
(f
OUT
≤
4 MHz)
Peak-to-peak period jitter
(4 MHz
≤
f
OUT
≤
16 MHz)
Peak-to-peak period jitter
(16 MHz
<
f
OUT
≤
50 MHz)
Peak-to-peak period jitter
(f
OUT
>
50 MHz)
Duty cycle for outputs, defined as t
2
÷
t
1[11]
f
OUT
> 66.67 MHz
Duty cycle for outputs, defined as t
2
÷
t
1[11]
f
OUT
≤
66.67 MHz
t
3
t
4
t
5
t
6
Rise time
Fall time
Output clock rise time
[12]
at C
L
=25 pF (15 pF
at 3.3V operation)
Output clock fall time
[12]
at C
L
=25 pF (15 pF
at 3.3V operation)
1
40%
45%
Min.
10
[100 MHz]
12.5
[80 MHz]
<0.5
<0.7
<400
<250
50%
50%
3
2.5
5
< 25
Typ.
Max.
2000
[500 KHz]
2000
[500 KHz]
1
1
500
350
60%
55%
5
4
40
50
ns
ns
MHz/
ms
ms
Unit
ns
ns
%
ns
ps
ps
Frequency Slew Rate Rate of change of frequency of CLKA
Power Up Stabiliza-
tion Time
Output clock stable time after power up
Switching Waveforms
All Outputs Duty Cycle and Rise/Fall Time
t
1
t
2
OUTPUT
2.4V
0.4V
t
3
2.4V
0.4V
t
4
3.3V
0V
Notes:
8. Guaranteed by design, not 100% tested.
9. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to
the application note: “Jitter in PLL-Based Systems.”
10. Reference Output duty cycle depends on XTALIN duty cycle.
11. Measured at 1.4V.
12. Measured between 0.4V and 2.4V.
Document #: 38-07136 Rev. **
Page 3 of 6
CY2081
Test Circuit
V
DD
0.1
µ
F
7
OUTPUTS
2
CLK output
C
LOAD
GND
Customer Configuration Request Procedure
The CY2081 is programmed at the wafer level, and is therefore
only available as a factory programmed device. There is no
field programming for the CY2081.
For CY2081 programmed configurations, design opportunities
must be 50 Ku per year in production. If the design opportunity
does not meet the factory minimums, the design can be imple-
mented using the CY2292 (3-PLLs, 16-SOIC, field program-
mable), or the CY22381 (3-PLLs, 8-SOIC, field programma-
ble).
For factory programmed samples, all requests must be sub-
mitted to your local Cypress FAE or sales representative. The
method to use to request factory configurations is:
Use CyClocks software. This software automatically calcu-
lates the output frequencies that can be generated by the
CY2081 and provides a printout of final pinout. Output fre-
quencies requested will be matched as closely as the internal
PLL divider and multiplier options allow. This printout and the
design entry file produced by CyClocks (<filename>.ENT) can
be submitted (in electronic format) to your local FAE or sales
representative. CyClocks software is available free of charge
from the Cypress website (http://www.cypress.com) or from
your local FAE or sales representative.
Once the custom request has been processed you will receive
a part number with a three-digit extension (e.g.,
CY2081SC-357) specific to the frequencies and pinout of your
device. This will be the part number used for samples requests
and production orders.
Ordering Information
Ordering Code
CY2081SC-XXX
CY2081SL-XXX
Note:
13. 0°C to +70°C
Package Name
S8
S8
Package Type
8-Pin (150-Mil) SOIC
8-Pin (150-Mil) SOIC
Operating Range
5.0V, Commercial
[13]
3.3V, Commercial
[13]
CyClocks is a trademark of Cypress Semiconductor Corporation.
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
京公网安备 11010802033920号
EEWORLD
