HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
Features:
x
x
x
IDT70V27S/L
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Industrial: 35ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
Low-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for bus
matching capability
Dual chip enables allow for depth expansion without
external logic
x
x
x
x
x
x
x
x
IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA
(fpBGA)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/W
R
UB
R
CE
0R
CE
1L
OE
L
LB
L
CE
1R
OE
R
LB
R
I/O
8-15L
I/O
0-7L
BUSY
L
(1,2)
I/O
Control
I/O
Control
I/O
8-15R
I/O
0-7R
BUSY
R
(1,2)
A
14L
A
0L
Address
Decoder
A
14L
A
0L
CE
0L
32Kx16
MEMORY
ARRAY
70V27
Address
Decoder
A
14R
A
0R
CE
1L
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
14R
A
0R
CE
0R
CE
1R
OE
R
R/
W
L
SEM
L
INT
L
(2)
R/
W
R
SEM
R
NOTES:
1)
BUSY
is an input as a Slave (M/S=V
IL
) and an output as a Master (M/S=V
IH
).
2)
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
M/
S
(2)
INT
R
3603 drw 01
(2)
JANUARY 2001
6.01
1
©2000 Integrated Device Technology, Inc.
DSC 3603/7
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Description:
The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (
CE
0
and
CE
1
) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 500mW of power. The IDT70V27
is packaged in a 100-pin Thin Quad Flatpack (TQFP), a 108-pin ceramic
Pin Grid Array (PGA), and a 144-pin Fine Pitch BGA (fp BGA).
Pin Configurations
(1,2,3)
INDEX
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
NC
NC
NC
LB
L
UB
L
CE
0L
CE
1L
SEM
L
Vcc
R/W
L
OE
L
GND
GND
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
NC
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
IDT70V27PF
PN100-1
(4)
100-PIN TQFP
TOP VIEW
(5)
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
NC
NC
NC
LB
R
UB
R
CE
0R
CE
1R
SEM
R
GND
R/W
R
OE
R
GND
GND
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
3603 drw 02
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
Vcc
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O1
L
I/O
0L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
Vcc
I/O
7R
I/O
8R
I/O
9R
NC
2
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Pin Configurations
(1,2,3)
(con't.)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
NC
B1
NC
B2
A
8L
B3
A
5L
B4
A
1L
B5
INT
L
B6
GND
BUSY
R
A
1R
B7
B8
B9
A
5R
B10
NC
B11
NC
B12
NC
B13
NC
C1
NC
C2
NC
C3
A
6L
C4
A
2L
C5
NC
C6
M/S
C7
INT
R
C8
A
2R
C9
A
6R
C10
NC
C11
NC
C12
NC
C13
A
10L
D1
A
9L
D2
NC
D3
A
7L
D4
A
3L
D5
NC
D6
NC
D7
D8
NC
A
3R
D9
A
7R
D10
A
9R
D11
A
10R
D12
A
11R
D13
A
14L
E1
A
13L
E2
A
12L
E3
A
11L
E4
A
4L
A
0L
BUSY
L
A
0R
A
4R
A
8R
E10
A
12R
E11
A
13R
E12
A
14R
E13
LB
L
F1
NC
F2
F3
NC
F4
NC
UB
L
G4
NC
F10
NC
F11
NC
F12
LB
R
F13
SEM
L
CE
1L
G1
G2
CE
0L
G3
IDT70V27BF
BF144-1
(4)
UB
R
G10
CE
0R
G11
CE
1R
SEM
R
G12
G13
V
CC
H1
V
CC
H2
V
CC
H3
H4
NC
144-Pin fpBGA
Top View
(5)
NC
H10
NC
H11
GND
H12
GND
H13
NC
J1
R/W
L
J2
J3
OE
L
J4
NC
NC
J10
OE
R
J11
R/W
R
J12
GND
J13
GND
K1
I/O
15L
K2
I/O
14L
I/0
13L
K3
K4
K5
K6
K7
K8
K9
I/O
13R
I/O
14R
I/O1
5R
GND
K10
K11
K12
K13
I/O
12L
L1
NC
L2
L3
NC
L4
NC
I/O
6L
L5
I/O
3L
L6
I/O
0R
L7
I/O
3R
L8
I/O
6R
I/O
11R
L9
L10
NC
L11
NC
L12
I/O
12R
L13
,
I/O
11L
I/O
10L
M1
M2
NC
M3
NC
M4
I/O
5L
M5
I/O
2L
M6
GND
M7
V
CC
M8
I/O
5R
M9
NC
M10
NC
M11
NC
M12
I/O
10R
M13
I/O
9L
N1
NC
N2
NC
N3
V
CC
N4
I/O
4L
N5
GND
N6
I/O
0L
N7
I/O
2R
N8
I/O
4R
N9
I/O
7R
N10
I/O
8R
N11
NC
N12
I/O
9R
N13
NC
NC
I/O
8L
I/O
7L
NC
I/O
1L
V
CC
I/O
1R
NC
V
CC
NC
NC
NC
3603 drw 02a
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 12mm x 12mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Pin Configurations
(1,2,3)
(con't.)
81
80
77
74
72
69
68
65
63
60
57
54
12
A
10R
84
A
11R
83
A
14R
78
76
NC
NC
79
UB
R
73
SEM
R
70
GND
67
GND
64
NC
61
I/O
13R
I/O
10R
59
56
NC
53
11
A
7R
87
A
8R
86
A
13R
82
LB
R
75
CE
1R
R/W
R
71
66
GND I/O
14R
I/O
12R
I/O
9R
62
58
55
51
NC
50
10
09
08
A
4R
90
A
5R
88
A
9R
85
A
12R
NC
CE
0R
OE
R
I/O
15R
I/O
11R
NC
52
I/O
8R
49
I/O
7R
47
A
1R
92
A
3R
91
A
6R
89
NC
48
Vcc
46
I/O
5R
45
INT
R
95
A
0R
94
A
2R
93
I/O
6R
44
I/O
4R
43
I/O
3R
42
07
06
GND
96
M/S
97
BUSY
R
98
IDT70V27G
G108-1
(4)
108-PIN PGA
TOP VIEW
(5)
I/O
2R
39
I/O
1R
40
I/O
0R
41
BUSY
L
INT
L
99
100
NC
102
I/O
1L
35
I/O
0L
37
GND
38
05
04
A
0L
101
A
1L
103
A
3L
106
I/O
4L
31
I/O
2L
34
GND
36
A
2L
104
A
4L
105
1
A
7L
4
8
12
17
21
25
Vcc
28
I/O
5L
32
I/O
3L
33
03
A
5L
107
2
A
6L
5
A
10L
7
A
13L
NC
10
CE
1L
13
GND
16
I/O
14L
I/O
10L
19
22
NC
24
I/O
7L
29
I/O
6L
30
02
A
8L
108
3
A
11L
6
A
14L
9
NC
LB
L
D
UB
L
11
SEM
L
14
OE
L
15
GND I/O
13L
18
20
I/O
11L
23
26
NC
I/O
8L
27
01
A
9L
A
A
12L
B
NC
C
CE
0L
E
Vcc
F
R/W
L
G
NC
H
I/O
15L
J
I/O
12L
K
I/O
9L
L
NC
M
3603 drw 03
INDEX
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21in x 1.21in x .16in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
14L
I/O
0L
- I/O
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
14R
I/O
0R
- I/O
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/S
V
CC
GND
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
3603 tbl 01
Names
4
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Truth Table I Chip Enable
(1,2,3)
CE
CE
0
V
IL
L
< 0.2V
V
IH
X
H
>V
CC
-0.2V
X
NOTES:
CE
1
V
IH
>V
CC
-0.2V
X
V
IL
X
<0.2V
Port Selected (TTL Active)
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Mode
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
3603 tbl 02
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels,
CE
is a reference only.
2. Port "A" and "B" references are located where
CE
is used.
3. "H" = V
IH
and "L" = V
IL
Truth Table II Non-Contention Read/Write Control
Inputs
(1)
CE
(2)
H
X
L
L
L
L
L
L
X
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
Outputs
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
3603 tbl 03
NOTES:
1. A
0L
— A
14L
≠
A
0R
— A
14R.
2. Refer to Chip Enable Truth Table.
Truth Table III Semaphore Read/Write Control
Inputs
(1)
CE
(2)
H
X
H
X
L
L
R/W
H
H
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
Outputs
I/O
8-15
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
______
I/O
0-7
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
______
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
3603 tbl 04
↑
↑
X
X
NOTES:
1. There are eight semaphore flags written to I/O
0
and read from all the I/Os (I/O
0
-I/O
15
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
5
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