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70V27L55BF

Description
Application Specific SRAM, 32KX16, 55ns, CMOS, PBGA144
Categorystorage    storage   
File Size179KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

70V27L55BF Overview

Application Specific SRAM, 32KX16, 55ns, CMOS, PBGA144

70V27L55BF Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
package instructionFBGA, BGA144,13X13,32
Reach Compliance Code_compli
Maximum access time55 ns
I/O typeCOMMON
JESD-30 codeS-PBGA-B144
JESD-609 codee0
memory density524288 bi
Memory IC TypeAPPLICATION SPECIFIC SRAM
memory width16
Humidity sensitivity level3
Number of ports2
Number of terminals144
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA144,13X13,32
Package shapeSQUARE
Package formGRID ARRAY, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply3.3 V
Certification statusNot Qualified
Maximum standby current0.003 A
Minimum standby current3 V
Maximum slew rate0.18 mA
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
Base Number Matches1
HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
Features:
IDT70V27S/L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/35ns (max.)
Low-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for bus
matching capability
Dual chip enables allow for depth expansion without
external logic
IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 100-pin Thin Quad Flatpack (TQFP), and 144-
pin Fine Pitch BGA (fpBGA)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/W
R
UB
R
CE
0R
CE
1L
OE
L
LB
L
CE
1R
OE
R
LB
R
I/O
8-15L
I/O
0-7L
BUSY
L
(1,2)
I/O
8-15R
I/O
Control
I/O
Control
I/O
0-7R
BUSY
R
(1,2)
,
A
14L
A
0L
Address
Decoder
A
14L
A
0L
CE
0L
32Kx16
MEMORY
ARRAY
70V27
Address
Decoder
A
14R
A
0R
CE
1L
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
14R
A
0R
CE
0R
CE
1R
OE
R
R/
W
L
SEM
L
INT
L
(2)
(2)
R/
W
R
SEM
R
(2)
INT
R
3603 drw 01
M/
S
NOTES:
1)
BUSY
is an input as a Slave (M/S=V
IL
) and an output as a Master (M/S=V
IH
).
2)
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
OCTOBER 2008
6.01
1
©2008 Integrated Device Technology, Inc.
DSC 3603/11
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