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74ACT11032DR

Description
Quadruple 2-Input Positive-OR Gates 16-SOIC -40 to 85
Categorylogic    logic   
File Size449KB,12 Pages
ManufacturerBel Fuse
Environmental Compliance
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74ACT11032DR Overview

Quadruple 2-Input Positive-OR Gates 16-SOIC -40 to 85

74ACT11032DR Parametric

Parameter NameAttribute value
Brand NameTexas Instruments
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerBel Fuse
Parts packaging codeSOIC
package instructionSOP-16
Contacts16
Reach Compliance Codecompliant
ECCN codeEAR99
Factory Lead Time1 week
Is SamacsysN
Other featuresCENTER PIN VCC AND GND
seriesACT
JESD-30 codeR-PDSO-G16
JESD-609 codee4
length9.9 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeOR GATE
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTR
Peak Reflow Temperature (Celsius)260
power supply5 V
Maximum supply current (ICC)0.04 mA
Prop。Delay @ Nom-Sup9 ns
propagation delay (tpd)8 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.91 mm
Base Number Matches1
74ACT11032
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCAS008C – JULY 1987 – REVISED APRIL 1996
D
D
D
D
D
Inputs Are TTL-Voltage Compatible
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages (D), Plastic Shrink
Small-Outline Packages (DB), Plastic Thin
Shrink Small-Outline Packages (PW), and
Standard Plastic 300-mil DIPs (N)
D, DB, N, OR PW PACKAGE
(TOP VIEW)
1A
1Y
2Y
GND
GND
3Y
4Y
4B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
2A
2B
V
CC
V
CC
3A
3B
4A
description
This device contains four independent 2-input OR gates. It performs the Boolean function Y = A + B or
Y
+
A
B in positive logic.
The 74ACT11032 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
H
X
L
B
X
H
L
OUTPUT
Y
H
H
L
logic symbol
1A
1B
2A
2B
3A
3B
4A
4B
1
16
15
14
11
10
9
8
7
4Y
6
3Y
3
2Y
logic diagram (positive logic)
2
1A
1Y
1B
2A
2B
3A
3B
4A
4B
4Y
3Y
2Y
1Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
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