LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
Check for Samples:
LMK04000, LMK04001, LMK04002, LMK04010, LMK04011, LMK04031, LMK04033
1
FEATURES
•
Cascaded PLLatinum™ PLL Architecture
– PLL1
– Phase Detector Rate of up to 40 MHz
– Integrated Low-Noise Crystal Oscillator
Circuit
– Dual Redundant Input Reference Clock
with LOS
– PLL2
– Normalized [1 Hz] PLL Noise Floor of -
224 dBc/Hz
– Phase Detector Rate up to 100 MHz
– Input Frequency-Doubler
– Integrated Low-Noise VCO
Ultra-Low RMS Jitter Performance
– 150 fs RMS Jitter (12 kHz – 20 MHz)
– 200 fs RMS Jitter (100 Hz – 20 MHz)
LVPECL/2VPECL, LVDS, and LVCMOS outputs
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•
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Support Clock Rates up to 1080 MHz
Default Clock Output (CLKout2) at power up
Five Dedicated Channel Divider and Delay
Blocks
Pin Compatible Family of Clocking Devices
Industrial Temperature Range: -40 to 85 °C
3.15 V to 3.45 V Operation
Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
23
APPLICATIONS
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•
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Data Converter Clocking
Wireless Infrastructure
Networking, SONET/SDH, DSLAM
Medical
Military / Aerospace
Test and Measurement
Video
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DESCRIPTION
The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and
distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a
cascaded PLLatinum™ architecture combined with an external crystal and varactor diode, the LMK04000 family
provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.
The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal
oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-
noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured
to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and
a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise
(offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as
the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be
optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the
VCXO module or crystal used in PLL1.
The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon
power up. The input block is equipped with loss of signal detection and automatic or manual selection of the
reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a
programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on
CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or
microcontroller that programs the jitter cleaner during the system power up sequence.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PLLatinum is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
Copyright © 2008–2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
www.ti.com
Connection Diagram
CLKout4*
CLKout3*
CLKout2*
CLKout1*
CLKout4
CLKout3
CLKout2
CLKout1
38
Vcc14
Vcc13
Vcc12
Vcc11
37
36
35
34
33
32
31
30
29
28
27
Bias
CLKin1_LOS
CLKin0_LOS
Vcc10
CPout2
Vcc9
Vcc8
OSCin*
OSCin
SYNC*
CLKin1*
CLKin1
26
25
13
Vcc3
14
CLKout0
15
CLKout0*
16
DLD_BYP
17
GND
18
Vcc4
19
Vcc5
20
CLKin0
21
CLKin0*
22
Vcc6
23
CPout1
24
Vcc7
48
GND
Fout
Vcc1
CLKuWire
DATAuWire
LEuWire
NC
Vcc2
LDObyp1
LDObyp2
GOE
LD
1
2
3
4
5
6
7
8
9
10
11
12
47
46
45
44
43
42
41
40
39
DAP
Figure 1. 48-Pin WQFN Package
Top View
PIN DESCRIPTIONS
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
4
Name(s)
GND
Fout
V
CC
1
CLKuWire
DATAuWire
LEuWire
NC
V
CC
2
LDObyp1
LDObyp2
GOE
LD
V
CC
3
CLKout0
CLKout0*
DLD_BYP
GND
V
CC
4
O
O
I
O
PWR
ANLG
ANLG
CMOS
CMOS
PWR
LVDS/LVPECL
LVDS/LVPECL
ANLG
GND
PWR
I
I
I
O
I/O
Type
GND
ANLG
PWR
CMOS
CMOS
CMOS
Description
Ground (For Fout Buffer)
VCO Frequency Output Port
Power Supply for VCO Output Buffer
Microwire Clock Input
Microwire Data Input
Microwire Latch Enable Input
No Connection
Power Supply for VCO
LDO Bypass, bypassed to ground with a 10 µF capacitor
LDO Bypass, bypassed to ground with a 0.1 µF
capacitor
Global Output Enable
Lock Detect and PLL multiplexer Output
Power Supply for CLKout0
Clock Channel 0 Output
Clock Channel 0* Output
DLD Bypass, bypassed to ground with a 0.47 µF
capacitor
Ground (Digital)
Power Supply for Digital
Copyright © 2008–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
PIN DESCRIPTIONS (continued)
Pin Number
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DAP
(1)
Name(s)
V
CC
5
CLKin0
CLKin0*
V
CC
6
CPout1
V
CC
7
CLKin1
CLKin1*
SYNC*
OSCin
OSCin*
V
CC
8
V
CC
9
CPout2
V
CC
10
CLKin0_LOS
CLKin1_LOS
Bias
V
CC
11
CLKout1
CLKout1*
V
CC
12
CLKout2
CLKout2*
V
CC
13
CLKout3
CLKout3*
V
CC
14
CLKout4
CLKout4*
DAP
O
O
O
O
O
O
O
O
O
O
I
O
I
I
I
I
I
O
I
I
I/O
Type
PWR
ANLG
ANLG
PWR
ANLG
PWR
ANLG
ANLG
CMOS
ANLG
ANLG
PWR
PWR
ANLG
PWR
LVCMOS
LVCMOS
ANLG
PWR
LVPECL/LVCMOS
LVPECL/LVCMOS
PWR
LVPECL/LVCMOS
LVPECL/LVCMOS
PWR
LVPECL
LVPECL
PWR
LVDS/LVPECL
LVDS/LVPECL
Description
Power Supply for CLKin buffers and PLL1 R-divider
Reference Clock Input Port for PLL1 - AC or DC
Coupled
(1)
Reference Clock Input Port for PLL1 (complimentary) -
AC or DC Coupled
(1)
Power Supply for PLL1 Phase Detector and Charge
Pump
Charge Pump1 Output
Power Supply for PLL1 N-Divider
Reference Clock Input Port for PLL1 - AC or DC
Coupled
(1)
Reference Clock Input Port for PLL1 (complimentary) -
AC or DC Coupled
(1)
Global Clock Output Synchronization
Reference oscillator Input for PLL2 - AC Coupled
Reference oscillator Input for PLL2 - AC Coupled
Power Supply for OSCin Buffer and PLL2 R-Divider
Power Supply for PLL2 Phase Detector and Charge
Pump
Charge Pump2 Output
Power Supply for VCO Divider and PLL2 N-Divider
Status of CLKin0 reference clock input
Status of CLKin1 reference clock input
Bias Bypass. AC coupled with 1 µF capacitor to Vcc1
Power Supply for CLKout1
Clock Channel 1 Output
Clock Channel 1* Output
Power Supply for CLKout2
Clock Channel 2 Output
Clock Channel 2* Output
Power Supply for CLKout3
Clock Channel 3 Output
Clock Channel 3* Output
Power Supply for CLKout4
Clock Channel 4 Output
Clock Channel 4* Output
DIE ATTACH PAD, connect to GND
The reference clock inputs may be either AC or DC coupled.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2008–2011, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links:
LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
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