Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
FEATURES
•
Low cost single-chip FSK receiver
•
Superheterodyne architecture with high integration level
•
Few external low cost components
•
Wide supply voltage range
•
Low power consumption
•
Wide frequency range, 150 to 450 MHz
•
High sensitivity
•
IF band determined by application
•
High selectivity
•
Very low spurious radiation,
−60
dBm
(meets FTZ 17TR2100)
•
Automotive temperature range
•
Power-down mode
•
SSOP20 package.
Applications
•
Keyless entry systems
•
Car alarm systems
•
Remote control systems
•
Security systems
•
Telemetry systems
•
Wireless data transmission
•
Domestic appliances.
QUICK REFERENCE DATA
SYMBOL
V
CC
I
CC
PARAMETER
supply voltage
supply current for
operating mode on
operating mode off
P
sens
sensitivity
V
PWD
= 0 V; R
2
= 560
Ω
V
PWD
= V
CC
f
i
= 433.92 MHz;
f
mod
= 250 Hz square wave;
∆f
=
±25
kHz; BER
≤
3%
2.0
−
−
3.4
3
−
CONDITIONS
MIN.
3.5
−
TYP.
GENERAL DESCRIPTION
UAA3202M
The UAA3202M is a fully integrated single-chip receiver,
primarily intended for use in VHF and UHF systems
employing direct Frequency Shift Keying (FSK)
modulation. The UAA3202M incorporates a SAW
stabilized local oscillator, balanced mixer, IF amplifier,
limiter, Received Signal Strength Indicator (RSSI), RSSI
comparator, FSK demodulator, data filter and data slicer.
The device features a power-down mode in order to
minimize the average receiver supply current.
MAX.
6
4.7
30
−94
V
UNIT
mA
µA
dBm
T
amb
operating ambient temperature
−40
−
+85
°C
ORDERING INFORMATION
TYPE
NUMBER
UAA3202M
PACKAGE
NAME
SSOP20
DESCRIPTION
plastic shrink small outline package; 20 leads; body width 5.3 mm
VERSION
SOT339-1
1997 Aug 12
2
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
FUNCTIONAL DESCRIPTION
The device is based on the superheterodyne architecture
incorporating a mixer, local oscillator, IF amplifier, limiter,
RSSI, RSSI comparator, FSK demodulator, data filter,
data slicer and power-down circuitry. The device employs
a low IF frequency of typically 1 MHz in order to allow IF
filtering by means of external low cost R, L and C
components. If image rejection is required it can be
achieved by applying a matching external front-end SAW
filter. The device provides a wide IF range of 300 kHz in
order to allow the use of a SAW stabilized oscillator.
The on-chip local oscillator provides the injection signal for
the mixer. Tuning of the on-chip local oscillator is not
necessary. The oscillator frequency is determined by an
external 1-port SAW resonator. The RF input signal is fed
to the mixer and down converted to the IF frequency. After
amplification and filtering the RF signal is applied to a
limiter. The IF filter order and characteristics are
determined by the external low cost R, L and C
components. The limiter amplifier provides a RSSI signal
which can be routed to an on-chip RSSI level comparator
in order to derive a field strength indication for external
use. The limited IF signal is fed to the FSK demodulator.
The demodulator centre frequency is determined by an
external capacitor. No alignment is necessary for the FSK
demodulator. After filtering the demodulated data signal is
fed to a data slicer and is made available at the data
output. The data filter characteristics are determined by
external capacitors. The data slicer employs an adaptive
slice reference in order to track frequency offsets.
The device is switched from power-down to operating
mode and vice versa by means of a control input.
Extremely low supply current is drawn when the device is
in power-down mode. Measures are taken to allow fast
receiver settling when the device is switched from
power-down to operating mode.
Mixer
The mixer is a single balanced emitter coupled mixer with
internal biasing. Matching of the RF source impedance to
the mixer input requires an external matching network.
Oscillator
The oscillator consists of an on-chip transistor in common
base configuration. An external tank and SAW resonator
determines the oscillator frequency. Oscillator alignment is
not necessary. Oscillator bias is controlled by an external
resistor.
Post mixer amplifier
UAA3202M
The Post Mixer Amplifier (PMA) is a differential input,
single-ended output amplifier. It separates the first and
second IF filters from each other. Amplifier gain is provided
in order to reduce the influence of the limiter noise figure
on the total noise figure.
Limiter
The limiter is a single-ended input multiple stage amplifier
with high total gain. Amplifier stability is achieved by
means of an external DC feedback capacitor, which is also
used to determine the lower limiter cut-off frequency.
An RSSI signal proportional to the limiter input signal is
provided.
IF filters
IF filtering with high selectivity is realized by means of
external low cost R, L and C components. The first IF filter
is located directly following the mixer output. An external
L/C network assembles a band-pass with low sensitivity in
order to meet the bandwidth of an elliptic low-pass filter
external to the device and is located in front of the limiter.
The filter source impedance is determined by the drive
impedance of the IF amplifier. In order to improve the IF
filter selectivity below the pass-band a high-pass
characteristic is added by means of a DC blocking
capacitor in front of the limiter input and by means of the
limiter DC feedback capacitor.
RSSI
The RSSI signal is a current proportional to the limiter input
level (RF input power). By means of an external resistor
the resulting RSSI voltage level is set in order to fit the
application. The RSSI voltage is available to external
circuits and is fed to the input of the RSSI level
comparator. For RSSI filtering an external capacitor is
connected.
RSSI level comparator
The RSSI level comparator compares the RSSI level with
a fixed and independent internal reference voltage. If the
RSSI level exceeds the internal reference voltage a logic
HIGH signal is generated. The level comparator provides
some hysteresis in order to avoid spurious oscillation.
The output of the level comparator is designed as an
open-collector with internal pull-up.
1997 Aug 12
5
京公网安备 11010802033920号
EEWORLD
