CMOS Logic Hex
Inverting Buffers
54HC4049
54HC4049
Logic Diagram
Memory
F
EATURES
:
• High speed CMOS logic hex inverting Buffers
• R
AD
-P
AK
® radiation hardened against natural space radia-
tion
• Single Event Effects:
- SEL: > 120 MeV/mg/cm2
• Total dose hardness:
• - > 100 Krad (Si), depending upon space mission
• Package:
-16 Pin R
AD
-P
AK
® Flat Pack
• Typical propagation delay:
- 6ns at V
CC
= 5V, C
L
= 15pF, TA = 25°C
• High-to-Low voltage level converter for up to V
I
= 16V
• Fanout (over temperature range)
-10 LSTTL loads (Standard Outputs)
-15 LSTTL loads (Bus Driver Outputs)
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• 2V to 6V operation
• High noise immunity
• -N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
D
ESCRIPTION
:
Maxwell Technologies' 54HC4049 high speed CMOS Logic
Hex Inverting Buffers features a greater than 100 krad(Si) total
dose tolerance, depending upon space misssion. These parts
have a modified input protection structure that enables them
to be used as logic level translators which will convert high-
level logic to a low-level logic while operating off the low-level
logic supply. For example, 15V input pulse levels can be
down-converted to 0V to 5V logic levels. The modified input
protection structure protects the input from negative electro-
static discharge. The 54HC4049 can be used as simple buff-
ers or inverters without level translation.
Maxwell Technologies' patented R
AD
-P
AK
® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
1000589
12.20.01 Rev1
All data sheets are subject to change without notice
1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2001 Maxwell Technologies.
All rights reserved.
CMOS Logic Hex Inverting Buffers
T
ABLE
1. 54HC4049 P
INOUT
D
ESCRIPTIONS
P
IN
1
8
13, 16
3, 5, 7, 9, 11, 14
2
4
6
10
12
15
S
YMBOL
V
CC
V
SS
NC
A-F
G=A
H=B
I=C
J=D
K=E
L=F
D
ESCRIPTION
Power supply
Ground
Not Connected
Inputs
Inverted Output
Inverted Output
Inverted Output
Inverted Output
Inverted Output
Inverted Output
54HC4049
Memory
T
ABLE
2. 54HC4049 A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Storage Temperature
Operating Temperature Range
DC Supply Voltage
DC Input Diode Current
For V
I
< -0.5V or V
I
> V
CC
+0.5V
DC Output Diode Current
For V
O
< -0.5V or V
O
> V
CC
+0.5V
DC Output Source or Sink Current per Output Pin
For V
O
> -0.5V or V
O
< V
CC
+0.5V
DC V
CC
or Ground Current
S
YMBOL
T
S
T
A
V
CC
I
IK
I
OK
I
O
I
CC
or I
GND
M
IN
-65
-55
-0.5
-20
-20
-25
-50
M
AX
150
125
7.0
+20
+20
+25
+50
U
NIT
°C
°C
V
mA
mA
mA
mA
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC
V
ARIATION
±10% of specified value in Table 5
1000589
12.20.01 Rev1
All data sheets are subject to change without notice
2
©2001 Maxwell Technologies.
All rights reserved.
CMOS Logic Hex Inverting Buffers
T
ABLE
4. 54HC4049 R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
Supply Voltage
DC Input or output Voltage
Input Rise and Fall Time
2V
4.5V
6V
Temperature Range
T
A
S
YMBOL
V
CC
V
I
, V
O
M
IN
2
0
--
1000
500
400
-55
125
M
AX
6
V
CC
54HC4049
U
NIT
V
V
ns
°C
T
ABLE
5. 54HC4049 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5V ±10%, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
High Level Output Voltage
CMOS Loads
S
YMBOL
V
OH
T
EST
C
ONDITIONS
V
I
= V
IH
or V
IL
, I
O
= -0.02mA
V
CC
= 2V
V
CC
= 4.5V
V
CC
= 6V
V
I
= V
IH
or V
IL
, I
O
= -4mA
V
CC
= 4.5V
V
I
= V
IH
or V
IL
, I
O
= -5.2mA
V
CC
= 6V
Low Level Output Voltage
CMOS Loads
V
OL
V
I
= V
IH
or V
IL
, I
O
= -0.02mA
V
CC
= 2V
V
CC
= 4.5V
V
CC
= 6V
V
I
= V
IH
or V
IL
, I
O
= 4mA
V
CC
= 4.5V
V
I
= V
IH
or V
IL
, I
O
= 5.2mA
V
CC
= 6V
High Level Input Voltage
V
IH
V
CC
= 2V
V
CC
= 4.5V
V
CC
= 6V
V
CC
= 2V
V
CC
= 4.5V
V
CC
= 6V
V
CC
= 6V, V
I
= V
CC
or GND
V
CC
= 6V, V
I
= 15V
+25°C
-55 to 125°C
+25°C
-55 to 125°C
1000589
12.20.01 Rev1
M
IN
1.9
4.4
5.9
+25°C
-55 to 125°C
+25°C
-55 to 125°C
3.98
3.7
5.48
5.2
M
AX
--
--
--
--
--
--
--
U
NIT
V
Memory
High Level Output Voltage
TTL Loads
V
0.1
0.1
0.1
+25°C
-55 to 125°C
+25°C
-55 to 125°C
0.26
0.4
0.26
0.4
1.5
3.15
4.2
--
--
--
--
--
--
--
--
--
--
0.5
1.35
1.8
±0.1
±1
±0.5
±5
V
--
--
Low Level Output Voltage
TTL Loads
Low Level Input Voltage
V
IL
V
Input Leakage Current
I
I
µA
All data sheets are subject to change without notice
3
©2001 Maxwell Technologies.
All rights reserved.
CMOS Logic Hex Inverting Buffers
T
ABLE
5. 54HC4049 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5V ±10%, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Quiescent Device Current
S
YMBOL
I
CC
T
EST
C
ONDITIONS
V
I
= V
CC
or GND, I
O
= 0mA
V
CC
= 6V
+25°C
-55 to 125°C
54HC4049
M
IN
--
--
M
AX
2
40
U
NIT
µA
T
ABLE
6. 54HC4049 AC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5V ±10%, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Propogation Delay
nA to nY
S
YMBOL
t
PLH,
t
PHL
C
L
= 50pF
V
CC
= 2V
V
CC
= 4.5V
V
CC
= 6V
Transition Times
(Figure 1)
t
TLH,
t
THL
C
L
= 50pF
V
CC
= 2V
V
CC
= 4.5V
V
CC
= 6V
T
EST
C
ONDITION
+25°C
--
-55 to 125°C
+25°C
-55 to 125°C
+25°C
-55 to 125°C
+25°C
--
-55 to 125°C
+25°C
-55 to 125°C
+25°C
-55 to 125°C
--
--
--
--
--
75
110
15
22
13
19
--
--
--
--
--
85
130
17
26
M
IN
M
AX
U
NIT
ns
Memory
14
22
ns
T
ABLE
7. 54HC4049 C
APACITANCE1
P
ARAMETER
Input Capacitance
Power Dissipation Capacitance
2, 3
1.
Guaranteed by design.
2. C
PD
is used to determine the dynamic power consumption, per gate.
3. P
D
= V
CC2
fi (C
PD
+ C
L
) where fi = Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
S
YMBOL
C
I
C
PD
V
CC
= 5V
T
EST
C
ONDITIONS
T
YP
10
35
U
NIT
pF
pF
1000589
12.20.01 Rev1
All data sheets are subject to change without notice
4
©2001 Maxwell Technologies.
All rights reserved.
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