This product has been retired and is not recommended for designs. For new designs, S29GL016A
supersedes Am29PL160C. Please refer to the S29GL-A family data sheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes
only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
22143
Revision
C
Amendment
7
Issue Date
May 9, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29PL160C
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
This product has been retired and is not recommended for designs. For new designs, S29GL016A supersedes Am29PL160C. Please refer to the S29GL-A family data sheet for specifica-
tions and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■
16 Mbit Page Mode device
— Byte (8-bit) or word (16-bit) mode selectable via
BYTE# pin
— Page size of 16 bytes/8 words: Fast page read
access from random locations within the page
■
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■
5 V-tolerant data, address, and control signals
■
High performance read access times
— Page access times as fast as 25 ns at industrial
temperature range
— Random access times as fast as 65 ns
■
Power consumption (typical values at 5 MHz)
— 30 mA read current
— 20 mA program/erase current
— 1 µA standby mode current
— 1 µA Automatic Sleep mode current
■
Flexible sector architecture
— Sector sizes: One 16 Kbyte, two 8 Kbyte, one
224 Kbyte, and seven sectors of 256 Kbytes
each
— Supports full chip erase
■
Bottom boot block configuration only
■
Sector Protection
— A hardware method of locking a sector to prevent
any program or erase operations within that
sector
— Sectors can be locked via programming
equipment
— Temporary Sector Unprotect command
sequence allows code changes in previously
locked sectors
■
Minimum 1 million write cycles guarantee
per sector
■
20-year data retention
■
Manufactured on 0.32 µm process technology
■
Software command-set compatible with JEDEC
standard
— Backward compatible with Am29F and Am29LV
families
■
CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■
Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Package Options
— 44-pin SO (mask-ROM compatible pinout)
— 48-pin TSOP
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
22143
Rev:
C
Amendment:
7
Issue Date:
May 9, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29PL160C is a 16 Mbit, 3.0 Volt-only Page
mode Flash memory device organized as 2,097,152
bytes or 1,048,576 words.The device is offered in a 44-
pin SO or a 48-pin TSOP package. The word-wide
data (x16) appears on DQ15–DQ0; the byte-wide (x8)
data appears on DQ7–DQ0. This device can be pro-
grammed in-system or with in standard
EPROM programmers. A 12.0 V V
PP
or 5.0 V
CC
are
not required for write or erase operations.
The device offers access times of 65, 70, and 90 ns, al-
lowing high speed microprocessors to operate without
wait states. To eliminate bus contention the device has
separate chip enable (CE#), write enable (WE#), and
output enable (OE#) controls.
The sector sizes are as follows: one 16 Kbyte, two
8 Kbyte, one 22 4 Kbyte an d seven sectors of
256 Kbytes each. The device is available in both top
and bottom boot versions.
automatically times the program pulse widths and
verifies proper cell margin. The
Unlock Bypass
mode
facilitates faster programming times by requiring only
two write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle)
status bits.
After a
program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
o r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a
programming equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Page Mode Features
The device is AC timing, pinout, and package
compat-
ible with 16 Mbit x 16 page mode Mask ROM.
The
page size is 8 words or 16 bytes.
After initial page access is accomplished, the page
mode operation provides fast read access speed of
random locations within that page.
Standard Flash Memory Features
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
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