LM27213
www.ti.com
SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013
LM27213 Single Phase Hysteretic Buck Controller
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LM27213
1
FEATURES
Ideal Load and Line Transient Responses
5V to 30V Input Range
On-Chip Gate Drive
Convenient CLK_EN# Signal
Input Under-Voltage Lockout
High Light-Load Efficiency
Adjustable Analog Soft Start
Peak Current Limit
Over-Voltage Protection
Error Correction for Good Static Accuracy
±1% DAC Accuracy Over Temperature
Interfaces with the LM2647 System Supply
Available in TSSOP or WQFN Packages
DESCRIPTION
The LM27213 is a single-phase synchronous buck
regulator controller designed to fully support a
portable microprocessor. On-chip gate drive makes
for a compact, single chip solution. Output currents in
excess of 25 Amps are possible.
The IC employs a current mode hysteretic control
mechanism. Inductor current is sensed through a low
value sense resistor.
The LM27213 will operate over an input voltage
range of 5V to 30V. The output voltage is
programmed through 6 Voltage Identification (VID)
pins and ranges from 0.700V to 1.708V in 64 steps.
Since the error in the output voltage directly sets the
inductor current, the dynamic response to a large,
fast load transient is close to a square wave. This is
optimal for mode transition requirements. Also, due to
the intrinsic input voltage feedforward characteristic of
hysteretic control, the line transient response is
excellent as well.
The IC provides cycle-by-cycle peak current limit,
over-voltage protection, and a power good signal.
The LM27213 fully supports the Stop CPU and Sleep
modes offered by some processors. When enabled,
the IC enters a power-saving “diode emulator” mode
which helps prolong battery runtime for portable
systems.
The LM27213 also has a soft start feature for the
external adjustment of soft start speed.
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2
APPLICATIONS
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•
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Core Voltage Supply for Low Power
Processors
Low Voltage High Current Buck Regulators
Benefits
Single Chip Core Power Solution
Minimum Output Capacitance Required
Low Cost, Compact Design
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2006–2013, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM27213
SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013
www.ti.com
Typical Application
VCC5
VDC
U1
V
DD
V1R7
VOVP
VBOOT
VSLP
DE_EN#
VID0
VID1
VID2
VID3
VID4
VID5
CLK_EN#
STP_CPU#
XPOK
STP
SLP
PGOOD
VDAC
VSTP
SGND
SS
DV
DD
CBOOT
HG
SW
LG
VCORE
LM27213
SRCK
PGND
DGND
+
ILIMREF
ILIM
SENS
CM
V
REF
CMPREF
Connection Diagram
CBOOT
HG
SW
NC
SRCK
NC
ILIM
ILIMREF
CMP
CMPREF
VREF
CLK_EN#
DGND
PGOOD
XPOK
SENSE
VOVP
P_Z2
P_Z1
NC
NC
P_Z0
SGND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PVDD
LG
NC
PGND
NC
NC
VRON
VID0
VID1
VID2
VID3
VID4
VID5
DE_EN#
STP_CPU#
SLP
VSTP
VDAC
NC
NC
VSLP
VBOOT
V1R7
SS
VID5
DE_EN#
STP_CPU#
SLP
VSTP
VDAC
NC
NC
VSLP
VBOOT
V1R7
SS
36
35
34
33
32
31
30
29
28
27
26
25
VID4
VID3
VID2
VID1
VID0
VRON
NC
NC
PGND
NC
LG
PVDD
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VDD
SGND
P_Z0
NC
NC
P_Z1
P_Z2
VOVP
SENSE
XPOK
PGOOD
DGND
Figure 1. Top View
48-Lead TSSOP
See DGG Package
Figure 2. Top View
48-Lead WQFN
See RHS0048A Package
2
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LM27213
Copyright © 2006–2013, Texas Instruments Incorporated
CBOOT
HG
SW
NC
SRCK
NC
ILIM
ILIMREF
CMP
CMPREF
VREF
CLK_EN#
1
2
3
4
5
6
7
8
9
10
11
12
LM27213
www.ti.com
SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013
PIN DESCRIPTIONS (TSSOP/LLP)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Name
CBOOT
HG
SW
NC
SRCK
NC
ILIM
ILIMREF
CMP
CMPREF
VREF
CLK_EN#
DGND
PGOOD
XPOK
SENSE
VOVP
P_Z2
P_Z1
NC
NC
P_Z0
SGND
VDD
SS
VIR7
VBOOT
VSLP
NC
NC
VDAC
VSTP
SLP
STP_CPU#
DE_EN#
VID5
VID4
VID3
VID2
Description
Connection for the high-side drive bootstrap capacitor
High-side FET gate drive output
Connect to switch node (drain of bottom power FET) to detect inductor current reversal. Also
serves as the return path for the high-side FET gate drive currents
No connect
Source Kelvin. Connect directly to source of low-side FET to detect negative inductor current
No connect
Over-current sense. Voltage between this pin and the regulator output is the voltage across
the current sense resistor
Current limit reference. Voltage between this pin and the regulator output sets the inductor
current limit level
Current sense. Voltage between this pin and the regulator output sets the cycle by cycle
inductor current
Inductor current reference. Voltage between this pin and the regulator output programs the
inductor current
Desired regulator output voltage under no load
Signal to start clock chip PLL locking. A low level indicates that the core supply is now stable
and the CPU can begin clocking
Digital ground
Power good flag. Open-drain output. Logic high when output voltage enters the power good
window and XPOK is asserted. Masked during transitions
Input that tells the LM27213 that the supply voltage for the Memory Controller Hub is up. The
LM27213 will regulate the output voltage to VBOOT until XPOK transitions to a high state.
PGOOD is forced low as long as this pin is low
Regulator output voltage sense. Connect directly to output
Over-voltage protection level. Connect this pin to the desired reference voltage to set the
trigger level for over-voltage protection
Factory reference trim, do not connect. This pin must float
Factory reference trim, do not connect. This pin must float
No connect
No connect
Factory reference trim, do not connect. This pin must float
Signal Ground
Chip power supply
Soft start, soft shutdown and slew rate control. Connect a capacitor between this pin and
ground to control the soft start and soft shutdown speed. The value of the capacitor will also
define the slew rate of the dynamic VID transitions
1.7V reference voltage
Initial output voltage desired after soft start completes. Connect this pin to the desired
reference level
Desired Voltage in Sleep Mode. Connect this pin to the desired reference level
No connect
No connect
Buffered Digital-to-Analog converter output
Desired output voltage in Stop CPU mode. Connect this pin to the desired reference level
When this pin is logic high, VREF voltage is equal to that on the VSLP pin
When this pin is logic low, VREF voltage is equal to that on the VSTP pin
Power saving mode trigger signal. Enables diode emulation
6th and most significant bit to program the output voltage
5th bit to program the output voltage
4th bit to program the output voltage
3rd bit to program the output voltage
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3
Copyright © 2006–2013, Texas Instruments Incorporated
LM27213
SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013
www.ti.com
PIN DESCRIPTIONS (TSSOP/LLP) (continued)
Pin
40
41
42
43
44
45
46
47
48
VID
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Name
VID1
VID0
VR_ON
NC
NC
PGND
NC
LG
PVDD
Description
2nd bit to program the output voltage
First and least significant bit to program the output voltage
Chip enable input
No connect
No connect
Power Ground. Connect to ground plane
Power ground connection
Low-side FET gate drive output
Power input for the gate drives
Voltage
(V)
1.708
1.692
1.676
1.660
1.644
1.628
1.612
1.596
1.580
1.564
1.548
1.532
1.516
1.500
1.484
1.468
1.452
1.436
1.420
1.404
1.388
1.372
1.356
1.340
1.324
1.308
1.292
1.276
1.260
1.244
1.228
1.212
VID
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Voltage
(V)
1.196
1.180
1.164
1.148
1.132
1.116
1.100
1.084
1.068
1.052
1.036
1.020
1.004
0.988
0.972
0.956
0.940
0.924
0.908
0.892
0.876
0.860
0.844
0.828
0.812
0.796
0.780
0.764
0.748
0.732
0.716
0.700
4
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Copyright © 2006–2013, Texas Instruments Incorporated
LM27213
www.ti.com
SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
VDD, DVDD XPOK, VR_ON, DE_EN#, VOVP, VBOOT, VID0 to VID5,
STP_CPU#, SLP, VSLP, VSTP, SENSE, CMP1, CMP2, CMPREF,
ILIM1, ILIM2, ILIMREF
PGOOD
SW to GND
(3)
-0.3V to 7V
-0.3V to 6V
-2V to 30V
-0.3V to 8V
CBOOT to SW
Power Dissipation
TSSOP, TA = 25°C,
WQFN, TA = 25°C,
(4)
(4)
1.56W
4.9W
+150°C
-20°C to +110°C
2kV
-65°C to +150°C
4sec, 260°C
10sec, 240°C
75sec, 219°C
Junction Temperature
Functional Temp. Range
ESD Rating
(5)
Storage Temp Range
Soldering Dwell Time, Temperature
Wave
Infrared
Vapor Phase
(1)
(2)
(3)
(4)
(5)
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. For ensured performance limits and associated test conditions, see the Electrical Characteristics
table. Functional temperature range is the range within which the device performs its intended functions, but not necessarily meeting the
limits specified in the Electrical Characteristic table.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The SW pin can have -2V to -0.5 volts applied for a maximum duty cycle of 10% with a minimum frequency of 1Hz. There is no duty
cycle or maximum period limitation for a SW pin voltage range of -0.5V to 30 Volts.
The maximum allowable power dissipation is calculated by using P
Dmax
= (T
JMAX
- T
A
) /θ
JA
, where T
JMAX
is the maximum junction
temperature, T
A
is the ambient temperature, and
θ
JA
is the junction-to-ambient thermal resistance of the specified package. The TSSOP
rating of 1.56W results from using 150°C, 25°C, and 80°C/W for T
JMAX
, T
A
, and
θ
JA
respectively. The
θ
JA
of 90°C/W represents the
worst-case condition with no heat sinking of the 48-Pin TSSOP. Heat sinking allows the safe dissipation of more power. The Absolute
Maximum power dissipation should be de-rated by 12.5mW per °C above 25°C ambient. The SQA rating of 5.2W results from using
150°C, 25°C, and 24.2°C/W for T
JMAX
, T
A
, and
θ
JA
respectively. The Absolute Maximum power dissipation should be de-rated by 41mW
per °C above 25°C ambient. The LM27213 actively limits its junction temperature to about 150°C.
For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged through a 1.5kΩ resistor.
(1)
Operating Ratings
VDD
Junction Temperature
Ambient Temperature
(1)
4.75V to 6V
-5°C to +110°C
-5°C to +105°C
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. For ensured performance limits and associated test conditions, see the Electrical Characteristics
table. Functional temperature range is the range within which the device performs its intended functions, but not necessarily meeting the
limits specified in the Electrical Characteristic table.
Electrical Characteristics
Specifications with standard typeface are for T
J
= 25°C, and those in
bold face type
apply over a junction temperature range
of -5°C to +110°C. Unless otherwise specified, VDD = 5V, SGND = DGND = PGND = SRCK = 0V, unless otherwise stated.
(1)
Symbol
Chip Supply
I
sd
I
q
(1)
Parameter
VDD Shutdown Current
VDD Normal Operating Current
Conditions
VR_ON = 0V, VDD = 6V
VR_ON = 3.3V
Min
Typ
1
3
Max
10
4.2
Units
µA
mA
All limits are specified at room temperature (standard face type) and at temperature extremes (bold face type). All room temperature
limits are 100% production tested. All limits at temperature extremes are ensured via correlation using Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
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