(VI–VO = 5.0 V; IO = 0.5 A for D2T and T packages; TJ = Tlow to Thigh [Note 1]; Imax and Pmax
[Note 2]; unless otherwise noted.)
Characteristics
Line Regulation (Note 3), TA = +25°C, 3.0 V
≤
VI–VO
≤
40 V
Load Regulation (Note 3), TA = +25°C, 10 mA
≤
IO
≤
Imax
VO
≤
5.0 V
VO
≥
5.0 V
Thermal Regulation, TA = +25°C (Note 6), 20 ms Pulse
Adjustment Pin Current
Adjustment Pin Current Change, 2.5 V
≤
VI–VO
≤
40 V,
10 mA
≤
IL
≤
Imax, PD
≤
Pmax
Reference Voltage, 3.0 V
≤
VI–VO
≤
40 V,
10 mA
≤
IO
≤
Imax, PD
≤
Pmax
Line Regulation (Note 3), 3.0 V
≤
VI–VO
≤
40 V
Load Regulation (Note 3), 10 mA
≤
IO
≤
Imax
VO
≤
5.0 V
VO
≥
5.0 V
Temperature Stability (Tlow
≤
TJ
≤
Thigh)
Minimum Load Current to Maintain Regulation (VI–VO = 40 V)
Maximum Output Current
VI–VO
≤
15 V, PD
≤
Pmax, T Package
VI–VO = 40 V, PD
≤
Pmax, TA = +25°C, T Package
RMS Noise, % of VO, TA = +25°C, 10 Hz
≤
f
≤
10 kHz
Ripple Rejection, VO = 10 V, f = 120 Hz (Note 4)
Without CAdj
CAdj = 10
µF
Long–Term Stability, TJ = Thigh (Note 5), TA = +25°C for
Endpoint Measurements
Thermal Resistance Junction to Case, T Package
4
3
1, 2
3
1
2
Figure
1
2
Symbol
Regline
Regload
–
–
Regtherm
IAdj
∆I
Adj
Vref
Regline
Regload
–
–
3
3
3
TS
ILmin
Imax
1.5
0.15
N
RR
–
66
3
S
R
θJC
–
–
65
80
0.3
5.0
–
–
1.0
–
%/1.0 k
Hrs.
°C/W
–
2.2
0.4
0.003
–
–
–
% VO
dB
–
–
20
0.3
0.7
3.5
70
1.5
–
10
mV
% VO
% VO
mA
A
–
–
–
1.2
–
5.0
0.1
0.03
50
0.2
1.25
0.02
25
0.5
0.07
100
5.0
1.3
0.07
mV
% VO
% VO/W
µA
µA
V
%V
Min
–
Typ
0.01
Max
0.04
Unit
%/V
NOTES:
1. Tlow to Thigh = 0° to +125°C, for LM317T, D2T. Tlow to Thigh = – 40° to +125°C, for LM317BT, BD2T.
2. Imax = 1.5 A, Pmax = 20 W
3. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately.
Pulse testing with low duty cycle is used.
4. CAdj, when used, is connected between the adjustment pin and ground.
5. Since Long–Term Stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability
from lot to lot.
6. Power dissipation within an IC voltage regulator produces a temperature gradient on the die, affecting individual IC components on the die. These
effects can be minimized by proper integrated circuit design and layout techniques. Thermal Regulation is the effect of these temperature gradients
on the output voltage and is expressed in percentage of output change per watt of power change in a specified time.
2
MOTOROLA ANALOG IC DEVICE DATA
LM317
Representative Schematic Diagram
Vin
31
0
310
230
120
5.6k
6.3V
170
6.7k
125k
135
12.4k
12k
5.0pF
6.8k
510
6.3V
160
200
13k
30
pF
6.3V
190
3.6k 5.8k
110
5.1k
30
pF
2.4k
12.5k
105
4.0
0.1
Vout
Adjust
This device contains 29 active transistors.
Figure 1. Line Regulation and
∆I
Adj/Line Test Circuit
VCC
*
VIH
VIL
Vin
LM317
* Pulse testing required.
*
1% Duty Cycle
*
is suggested.
Adjust
Cin
0.1
µF
IAdj
R1
240
1%
Line Regulation (% V)
Vout
+
|V
–V |
OH OL
x 100
|V |
OL
VOH
VOL
+
CO
1.0
µF
RL
R2
1%
MOTOROLA ANALOG IC DEVICE DATA
3
LM317
Figure 2. Load Regulation and
∆I
Adj/Load Test Circuit
VI
Vin
LM317
Vout
IL
RL
(max Load)
*
+
IAdj
CO
1.0
µF
VO (min Load)
VO (max Load)
RL
(min Load)
Adjust
Cin
0.1
µF
R1
240
1%
R2
1%
* Pulse testing required.
*
1% Duty Cycle is suggested.
Load Regulation (mV) = VO (min Load) – VO (max Load)
Load Regulation (% VO) =
VO (min Load) – VO (max Load)
x 100
VO (min Load)
Figure 3. Standard Test Circuit
Vin
LM317
Vout
IL
Adjust
VI
Cin
0.1
µF
R1
IAdj
240
1%
Vref
+
CO
1.0
µF
RL
VO
ISET
R2
1%
* Pulse testing required.
*
1% Duty Cycle is suggested.
To Calculate R2: Vout = ISET R2 + 1.250 V
To Calculate R2:
Assume ISET = 5.25 mA
Figure 4. Ripple Rejection Test Circuit
24 V
14 V
f = 120 Hz
Vin
LM317
Vout
Adjust
Cin
0.1
µF
R1
240
1%
D1*
1N4002
+
CO
1.0
µF
RL
VO
Vout = 10 V
R2
1.65 k
1%
+
CAdj
10
µF
* D1 Discharges CAdj if output is shorted to Ground.
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