Preliminary
GS816218A(B/D)/GS816236A(B/D)/GS816272A(C)
119-, 165-, & 209-Pin BGA
Commercial Temp
Industrial Temp
Features
1M x 18, 512K x 36, 256K x 72
300 MHz–200 MHz
1.8 V or 2.5 V V
DD
18Mb S/DCD Sync Burst SRAMs
1.8 V or 2.5 V I/O
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-, 165-, and 209-bump BGA package
Flow Through/Pipeline Reads
SCD and DCD Pipelined Reads
Pipeline
3-1-1-1
2.5 V
1.8 V
Flow
Through
2-1-1-1
2.5 V
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
Curr
(x72)
Curr
(x18)
Curr
(x36)
Curr
(x72)
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
Curr
(x72)
Curr
(x18)
Curr
(x36)
Curr
(x72)
-300 -275 -250 -225 -200 Unit
2.2 2.4 2.5 2.7 3.0 ns
3.3 3.6 4.0 4.4 5.0 ns
320
375
475
320
370
470
5.0
5.0
220
265
315
220
265
315
300
345
445
300
340
435
5.25
5.25
215
260
305
215
260
305
275
320
410
275
315
400
5.5
5.5
210
245
295
210
245
295
250
295
380
250
285
365
6.0
6.0
200
235
285
200
235
285
230
265
335
225
260
325
6.5
6.5
190
225
260
190
225
260
mA
mA
mA
mA
mA
mA
ns
ns
mA
mA
mA
mA
mA
mA
The GS816218/36/72A is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Byte Write and Global Write
FLXDrive™
1.8 V
Functional Description
Applications
The GS816218/36/72A is a 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
Controls
The GS816218/36/72A operates on a 2.5 V or 1.8 V power supply.
All input are 1.8 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 1.8 V and 2.5 V compatible.
Rev: 1.02a 9/2002
1/41
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS816218A(B/D)/GS816236A(B/D)/GS816272A(C)
GS816272A 209-Bump BGA Pin Description
Symbol
A
0
, A
1
An
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
DQ
E1
–DQ
E9
DQ
F1
–DQ
F9
DQ
G1
–DQ
G9
DQ
H1
–DQ
H9
B
A
, B
B
, B
C
,B
D,
B
E
, B
F
, B
G
,B
H
NC
CK
GW
E
1,
E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
SCD
MCH
MCL
PE
BW
ZQ
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
Rev: 1.02a 9/2002
I
I
I
I
I
O
I
I
I
I
3/41
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
I/O
Data Input and Output pins
I
—
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D,
DQ
E
,
DQ
F
, DQ
G
, DQ
H
I/Os; active low
No Connect
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
Must Connect Low
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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