Preliminary
RF2469
W-CDMA AND PCS LOW NOISE
AMPLIFIER/MIXER DOWNCONVERTER
8
Typical Applications
• W-CDMA Handsets
• PCS Handsets
• General Purpose Downconverter
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
Product Description
The RF2469 is a receiver front-end designed for the
receive section of W-CDMA and PCS applications. It is
designed to amplify and downconvert RF signals while
providing 23dB of stepped gain control range and fea-
tures digital control of the LNA gain and mixer gain. A fur-
ther feature of the chip is adjustable IIP3 of the LNA and
mixer using an off-chip current setting resistor. Noise Fig-
ure, IP3, and other specs are designed to be compatible
with W-CDMA and PCS communications. The IC is man-
ufactured on an advanced Gallium Arsenide Heterojunc-
tion Bipolar Transistor (GaAs HBT) process and
packaged in a 20-pin, leadless chip carrier with an
exposed die flag.
1.00
0.90
0.60
0.24 typ
4.00
sq.
4 PLCS
0.65
0.30
3
0.20
2.10
sq.
12°
MAX
0.05
Dimensions in mm.
0.75
0.50
0.50
Note orientation of package.
0.23
0.13
4 PLCS
NOTES:
1 Shaded lead is Pin 1.
2 Pin 1 identifier must exist on top surface of package by identification
mark or feature on the package body. Exact shape and size is optional.
8
FRONT-ENDS
Dimension applies to plated terminal: to be measured between 0.02 mm
and 0.25 mm from terminal end.
4 Package Warpage: 0.05 mm max.
5 Die Thickness Allowable: 0.305 mm max.
3
Optimum Technology Matching® Applied
Si BJT
Si Bi-CMOS
ü
GaAs HBT
SiGe HBT
LNA1 IN
VCC1
GND
Package Style: LCC, 20-Pin, 4x4
GaAs MESFET
Si CMOS
ENABLE
Features
• Complete Receiver Front-End
• Stepped LNA/Mixer Gain Control
• Adjustable LNA/Mixer Bias Current
• 23dB Maximum Cascade Gain
• 2.5dB Noise Figure at Maximum
Cascade Gain
20
LNA1 OUT
GND
VCC1
VCC1
LNA2 IN
1
2
3
4
5
6
LNA2 OUT
19
18
17
VCC1
16
15
14
LNA1 BYP
LNA2
BYP
GND
VCC1
LO IN
Logic
Control
13
12
11
7
GND
8
MIX IN
9
IF+
10
IF-
Ordering Information
RF2469
RF2469 PCBA
W-CDMA and PCS Low Noise Amplifier/Mixer Down-
converter
Fully Assembled Evaluation Board
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Rev A5 010717
8-33
RF2469
Absolute Maximum Ratings
Parameter
Operating Ambient Temperature
Storage Temperature
Preliminary
Rating
-40 to +85
-40 to +150
Unit
°C
°C
Caution!
ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Parameter
Overall
RF Frequency Range
LO Frequency Range
IF Frequency Range
Specification
Min.
Typ.
Max.
2110 to 2170
2300 to 2360
190
Unit
Condition
T=25°C, V
CC
=2.78V, RF=2140MHz,
LO=2330MHz @ -10dBm
MHz
MHz
MHz
1st LNA current setting resistor (R1) is
1.1kΩ. 1st LNA current and IIP3 are adjust-
able via R1.
LNA 1
Gain
Noise Figure
Input IP3
Input VSWR
Output VSWR
P1dB
Current
9
+7.0
10
1.45
+10.0
<2:1
<2:1
-3
4.5
-2
2
+25.0
<2:1
<2:1
1.6
11
1.6
dB
dB
dBm
dB
mA
0
2.4
dB
dB
dBm
See LNA P1dB Compression Point section.
8
FRONT-ENDS
LNA 1 Bypass
Gain
Noise Figure
Input IP3
Input VSWR
Output VSWR
Current
-5
+20.0
mA
Single-ended.
Optimum LO Drive -10dBm to -5dBm.
Local Oscillator Input
Input Level
LO to IF Isolation
-10
+38
dBm
dB
Mixer/LNA2 BYP High
Gain
Noise Figure
Input IP3
Input IP2
15
-7.0
+11.0
17
4.5
-3.0
+14.0
dB
dB
dBm
dBm
T=25°C, V
CC
=2.78V, RF=2140MHz,
LO=2330MHz@-10dBm, LNA2BYP=1,
EN=1
Mixer/LNA2 BYP Low
Gain
Noise Figure
Input IP3
Input IP2
4
+2.0
+19.0
6
10.5
+4.0
+22.0
dB
dB
dBm
dBm
LNA 2 current setting resistor (R2) is 2.4kΩ
LNA 2 current and IIP3 are adjustable via R2
T=25°C, V
CC
=2.78V, RF=2140MHz,
LNA2BYP=0, EN =1
LNA 2 current setting resistor (R2) is 2.4kΩ
LNA 2 current and IIP3 are adjustable via R2
8-34
Rev A5 010717
Preliminary
Parameter
Cascade - Condition 1
Gain
Noise Figure
Input IP3
Current Consumption*
24.5
2.55
-10.5
18.6
dB
dB
dBm
mA
RF2469
Specification
Min.
Typ.
Max.
Unit
Condition
LNA1 BYP high, LNA2 BYP high,
ENABLE high. Assuming 2.5dB filter loss.
23
Cascade - Condition 2
Gain
Noise Figure
Input IP3
Current Consumption*
13.5
5.2
-3.5
17
dB
dB
dBm
mA
LNA1 BYP high, LNA2 BYP low,
ENABLE high. Assuming 2.5dB filter loss.
17.5
Cascade - Condition 3
Gain
Noise Figure
Input IP3
Current Consumption*
12.5
9
+1.4
14
dB
dB
dBm
mA
LNA1 BYP low, LNA2 BYP high,
ENABLE high. Assuming 2.5dB filter loss.
15
Cascade - Condition 4
Gain
Noise Figure
Input IP3
Current Consumption*
1.50
15
+8.2
12.5
dB
dB
dBm
mA
LNA1 BYP low, LNA2 BYP low,
ENABLE High. Assuming 2.5dB filter loss.
13.5
8
FRONT-ENDS
Power Supply
Voltage
2.7
2.75
3.3
V
*RF2469 is a very flexible device. Customers may choose different current consumption (see Low Current Configuration section).
Rev A5 010717
8-35
RF2469
Pin
1
Function
LNA1 OUT
Description
LNA output pin. This is an open-collector output. Externally matched to
50Ω.
Preliminary
Interface Schematic
LNA1 OUT
2
3
GND
VCC1
This pin is connected to the ground plane.
Supply voltage for LNA1. An external resistor is placed in series with
this pin to adjust the current and IIP3 of LNA1. A nominal value of
1.1kΩ sets the LNA1 current to 4.5mA with a minimum IIP3 of +7dBm.
External RF bypassing is required. The trace length between the
bypass caps and the pin should be minimized. Connect ground sides of
caps directly to ground.
Supply voltage for LNA2. An external resistor is placed in series with
this pin to adjust the current and IIP3 of LNA2. A nominal value of
2.4kΩ sets the LNA2 current to 1.6mA. External RF bypassing is
required. The trace length between the bypass caps and the pin should
be minimized. Connect ground sides of caps directly to ground.
RF input to LNA2. This pin is internally DC-biased and, if it is con-
nected to a device with DC present, should be DC-blocked with a
capacitor suitable for the frequency of operation.
4
VCC1
5
LNA2 IN
LNA2 IN
6
LNA2 OUT
LNA output pin. This is an open-collector output. In normal operation,
this pin is externally cascaded with pin 8 (MIX IN).
LNA2 OUT
8
FRONT-ENDS
7
8
GND
MIX IN
9
IF+
Ground connection. For best performance, keep traces physically short
and connect directly to ground plane.
Mixer RF input pin. This pin requires a DC path to ground. In normal
operation, this pin is externally cascaded with pin 6 (LNA2 OUT). The
external match ensures a conjugate match between pin 6 and pin 8
while providing a DC path to ground for pin 8 and a DC-block between
pin 8 and pin 6.
IF output pin. The output is balanced. A current combiner external net-
work performs a differential to single-ended conversion and sets the
output impedance. There must be a DC path from V
CC
to this pin. This
is normally achieved with the current combiner network. A DC blocking
cap must be present if the IF filter input has a DC path to ground.
Same as pin 9, except complementary output.
Mixer LO single-ended input. The pin is internally DC-blocked. External
matching sets impedance.
Supply voltage for LO buffer. External RF bypassing is required. The
trace length between the bypass caps and the pin should be minimized.
Connect ground sides of caps directly to ground.
This pin is connected to the ground plane.
Logic control for LNA2 gain. A logic high (>2.4V) places LNA2 in the
high gain mode. A logic low (<0.3V) place LNA2 in the bypass mode.
See pin 9.
IF+
IF-
10
11
12
13
14
IF-
LO IN
VCC1
GND
LNA2 BYP
LO IN
32 kΩ
LNA2 BYP
8-36
Rev A5 010717
Preliminary
Pin
15
16
17
Function
LNA1 BYP
ENABLE
VCC1
Description
Logic control for LNA1 gain. A logic high (>2.4V) places LNA1 in the
high gain mode. A logic low (<0.3V) place LNA1 in the bypass mode.
A logic control for mixer and LO buffer. A logic high (>2.4V) turn the
mixer and LO buffer on. A logic low (<0.3V) disable the mixer and LO
buffer.
Supply voltage for the mixer. An external resistor is place in series with
this pin to adjust the mixer current. A nominal value of 1000Ω set the
mixer current to ~10mA. External RF bypassing is required. The trace
length between the bypass caps and the pin should be minimized. Con-
nect ground sides of caps directly to ground.
Supply voltage for IC. External RF bypassing is required. The trace
length between the bypass caps and the pin should be minimized. Con-
nect ground sides of caps directly to ground.
RF input to LNA1. This pin is internally DC-biased and, if it is con-
nected to a device with DC present, should be DC-blocked with a
capacitor suitable for the frequency of operation.
Ground connection. For best performance, keep traces physically short
and connect directly to ground plane.
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias.
RF2469
Interface Schematic
32 kΩ
LNA1 BYP
32 kΩ
ENABLE
18
19
VCC1
LNA1 IN
LNA1 IN
20
Pkg
Base
GND
GND
8
FRONT-ENDS
Rev A5 010717
8-37
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