MC14051BDTEL datasheet, PDF - EEWORLD Datasheet

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MC14051BDTEL: Description8-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16, PLASTIC, TSSOP-16; CategoryAnalog mixed-signal IC The signal circuit; File Size342KB，12 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn; Environmental Compliance

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MC14051BDTEL Overview

8-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16, PLASTIC, TSSOP-16

MC14051BDTEL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ON Semiconductor
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP16,.25
Contacts	16
Reach Compliance Code	unknown
Analog Integrated Circuits - Other Types	SINGLE-ENDED MULTIPLEXER
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	5 mm
Number of channels	8
Number of functions	1
Number of terminals	16
Nominal off-state isolation	50 dB
On-state resistance matching specifications	25 Ω
Maximum on-state resistance (Ron)	1050 Ω
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5/15 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum signal current	0.025 A
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Maximum disconnect time	700 ns
Maximum connection time	700 ns
switch	BREAK-BEFORE-MAKE
technology	CMOS
Temperature level	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm

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MC14051B, MC14052B,

MC14053B

Analog

Multiplexers/Demultiplexers

The MC14051B, MC14052B, and MC14053B analog multiplexers

are digitally–controlled analog switches. The MC14051B effectively

implements an SP8T solid state switch, the MC14052B a DP4T, and

the MC14053B a Triple SPDT. All three devices feature low ON

impedance and very low OFF leakage current. Control of analog

signals up to the complete supply voltage range can be achieved.

http://onsemi.com

MARKING

DIAGRAMS

PDIP–16

P SUFFIX

CASE 648

MC140XXBCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

TSSOP–16

DT SUFFIX

CASE 948F

, V

out

DC Supply Voltage (Referenced

to V

, V

≥

)

Input or Output Voltage Range

(DC or Transient) (Referen–

ced to V

for Control Inputs

and V

for Switch I/O)

Input Current (DC or Transient)

per Control Pin

Switch Through Current

Power Dissipation,

per Package (Note 2.)

Ambient Temperature Range

Storage Temperature Range

Lead Temperature

(8–Second Soldering)

– 0.5 to +18.0

– 0.5 to V

+ 0.5

SOEIAJ–16

F SUFFIX

CASE 966

°C

= Specific Device Code

= Assembly Location

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

MC140XXB

AWLYWW

0XXB

ALYW

140XXB

AWLYWW

•

Triple Diode Protection on Control Inputs

Switch Function is Break Before Make

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Analog Voltage Range (V

– V

) = 3.0 to 18 V

Note: V

must be V

Linearized Transfer Characteristics

Low–noise – 12 nV/√Cycle, f

≥

1.0 kHz Typical

Pin–for–Pin Replacement for CD4051, CD4052, and CD4053

For 4PDT Switch, See MC14551B

For Lower R

, Use the HC4051, HC4052, or HC4053 High–Speed

CMOS Devices

MAXIMUM RATINGS

(Note 1.)

Symbol

Parameter

Value

Unit

stg

500

– 55 to +125

– 65 to +150

260

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 12 of this data sheet.

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high–impedance circuit. For proper operation, V

and V

out

should be constrained

to the range V

or V

out

)

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V

, V

or V

). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

Publication Order Number:

MC14051B/D

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