application
INFO
available
UCC15701/2
UCC25701/2
UCC35701/2
Advanced Voltage Mode Pulse Width Modulator
FEATURES
700kHz Operation
Integrated Oscillator/ Voltage Feed
Forward Compensation
Accurate Duty Cycle Limit
Accurate Volt-second Clamp
Optocoupler Interface
Fault Counting Shutdown
Fault Latch off or Automatic Shutdown
Soft Stop Optimized for Synchronous
Rectification
1A Peak Gate Drive Output
130mA Start-up Current
750mA Operating Current
DESCRIPTION
The UCC35701/UCC35702 family of pulse width modulators is intended for
isolated switching power supplies using primary side control. They can be
used for both off-line applications and DC/DC converter designs such as in
a distributed power system architecture or as a telecom power source.
The devices feature low startup current, allowing for efficient off-line start-
ing, yet have sufficient output drive to switch power MOSFETs in excess of
500kHz.
Voltage feed forward compensation is operational over a 5:1 input range
and provides fast and accurate response to input voltage changes over a
4:1 range. An accurate volt-second clamp and maximum duty cycle limit
are also featured.
Fault protection is provided by pulse by pulse current limiting as well as the
ability to latch off after a programmable number of repetitive faults has oc-
curred.
Two UVLO options are offered. UCC35701 family has turn-on and turn-off
thresholds of 13V/9V and UCC35702 family has thresholds of 9.6V/8.8V.
The UCC35701/2 and the UCC25701/2 are offered in the 14 pin SOIC (D),
14 pin PDIP (N) or in 14 pin TSSOP (PW) packages. The UCC15701/2 is
offered in the 14 pin CDIP (J) package.
TYPICAL APPLICATION DIAGRAM
V
IN
S UP P LY
R1
6
R3
VREF
R4
9
R5
C
S
14
C
F
1
R
F
C3
12
R8
8
FB
GND
13
R11
C5
R12
C6
C7
R13
R14
R15
UDG-98005-1
R2
R6
VFF
RT
UCC35701
10
CT
C1
VS CLAMP
S YNC
SS
COUNT
VREF
P GND
5
RGND
OUT
ILIM
4
2
C2
RCS
R8
R10
VDD
3
R7
7
C
T
C6 V
OUT
C4
11
V
IN
RETURN
V
OUT
SLUS293C - JANUARY 2000 - REVISED JUNE 2005
UCC15701/2
UCC25701/2
UCC35701/2
ABSOLUTE MAXIMUM RATINGS
Supply voltage (Supply current limited to 20mA) . . . . . . . . 15V
Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Input pins ( ILIM,VFF,RT,CT,VSCLAMP,SYNC,SS, FB) . . . 6V
Output Current (OUT) DC. . . . . . . . . . . . . . . . . . . . . +/–180mA
Output Current (OUT) Pulse (0.5ms) . . . . . . . . . . . . . . +/–1.2A
Storage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . +300°C
Note:
All voltages are with respect to GND. Currents are posi-
tive into the specified terminal. Consult Packaging Section of
the Databook for thermal limitations and considerations of
packages.
ORDERING INFORMATION
UVLO
Option
13V / 9V
–55°C to +125°C
9.6V / 8.8V
13V / 9V
–40°C to +85°C
9.6V / 8.8V
T
A
= T
J
Package
CDIP-14
CDIP-14
SOIC-14
PDIP-14
TSSOP-14
SOIC-14
PDIP-14
TSSOP-14
SOIC-14
PDIP-14
TSSOP-14
SOIC-14
PDIP-14
TSSOP-14
Part Number
UCC15701J
UCC15702J
UCC25701D
UCC25701N
UCC25701PW
UCC25702D
UCC25702N
UCC25702PW
UCC35701D
UCC35701N
UCC35701PW
UCC35702D
UCC35702N
UCC35702PW
13V / 9V
0°C to +70°C
9.6V / 8.8V
CONNECTION DIAGRAMS
DIL-14, SOIC-14, TSSOP-14 (TOP VIEW)
N or J, D, PW PACKAGE
COUNT
ILIM
VDD
OUT
P GND
VFF
RT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SS
GND
VREF
S YNC
CT
VS CLAMP
FB
The D and PW packages are available taped and reeled. Add
TR suffix to the device type (e.g., UCC35701DTR).
ELECTRICAL CHARACTERISTICS:
Unless otherwise specified, V
DD
= 11V, RT = 60.4k, C
T
= 330pF, C
REF
= C
VDD
=
0.1m F, V
FF
= 2.0V, and no load on the outputs.
PARAMETER
UVLO Section
Start Threshold
Stop Threshold
Hysteresis
Supply Current
Start-up Current
I
DD
Active
V
DD
Clamp Voltage
V
DD
Clamp – Start Threshold
Voltage Reference
V
REF
Line Regulation
Load Regulation
Short Circuit Current
TEST CONDITIONS
(UCCX5701)
(UCCX5702)
(UCCX5701)
(UCCX5702)
(UCCX5701)
(UCCX5702)
(UCCX5701) V
DD
= 11V, V
DD
Comparator Off
(UCCX5702) V
DD
= 8V, V
DD
Comparator Off
V
DD
Comparator On
(UCCX5701) I
DD
= 10mA
(UCCX5702) I
DD
= 10mA
(UCCX5701)
(UCCX5702)
V
DD
= 10V to 13V, I
VREF
= 0mA to 2mA
V
DD
= 10V to 13V
I
VREF
= 0mA to 2mA
V
REF
= 0V, T
J
= 25°C
MIN
12
8.8
8
8.0
3
0.3
TYP
13
9.6
9
8.8
4
0.8
130
120
0.75
14.3
13.8
1.3
4.2
5
20
2
20
MAX
14
10.4
10
9.6
UNITS
V
V
V
V
V
V
mA
mA
mA
V
V
V
V
V
mV
mV
mA
13.5
13
200
190
1.5
15
15
4.9
5.1
50
2
UCC15701/2
UCC25701/2
UCC35701/2
DETAILED BLOCK DIAGRAM
2*I
RT
S
VFF
RT
CT
6
Q
7
10
I
RT
P WM
0.7V
+
FB
8
1.5R
R
0.2V
VALLEY
S
R
D
5
VS CLAMP
9
4V
V
REF
I
SS
14
0.6V
ILIM
2
0.2V
D
P WM
S S DONE
COUNT
1
R
4V
Q
CURRENT FAULT
CURRENT LIMIT
V
REF
I
R
S
D
Q
25*I
R
S
D
FAULT
LATCH
5.0V
REF
12 VREF
Q
0.6V
S S DONE
HIGH LINE
LOW LINE
RUN
13/9V (35701)
9.6/8.8V (35702)
4.5V
P GND
Q
4
OUT
P EAK
3
VDD
R
D
3m A
11
S YNC
0.2V
VDD
13 GND
S HUTDOWN
LATCH
UDG-98004
PIN DESCRIPTIONS
VDD:
Power supply pin. A shunt regulator limits supply
voltage to 14V typical at 10mA shunt current.
PGND:
Power Ground. Ground return for output driver
and currents.
GND:
Analog Ground. Ground return for all other circuits.
This pin must be connected directly to PGND on the
board.
OUT:
Gate drive output. Output resistance is 10W maxi-
mum.
VFF:
Voltage feedforward pin. This pin connects to the
power supply input voltage through a resistive divider
and provides feedforward compensation over a 0.8V to
3.2V range. A voltage greater than 4.0V or less than
0.6V on this pin initiates a soft stop cycle.
4
RT:
The voltage on this pin mirrors VFF over a 0.8V to
3.2V range. A resistor to ground sets the ramp capacitor
charge current. The resistor value should be between
20k and 200k.
CT:
A capacitor to ground provides the oscillator/
feedforward sawtooth waveform. Charge current is 2
·
I
RT
, resulting in a CT slope proportional to the input volt-
age. The ramp voltage range is GND to V
RT
.
Period and oscillator frequency is given by:
T
=
F
»
V
R T
·
C
T
+
t
DIS CH
»
0 . 5
·
R
T
·
C
T
2
·
I
R T
2
R T
·
CT
UCC15701/2
UCC25701/2
UCC35701/2
PIN DESCRIPTIONS (cont.)
VSCLAMP:
Voltage at this pin is compared to the CT
voltage, providing a constant volt-second limit. The com-
parator output terminates the PWM pulse when the ramp
voltage exceeds VSCLAMP. The maximum on time is
given by:
V
·
CT
t
ON
=
VS CLAMP
2
·
I
R T
The maximum duty cycle limit is given by:
D
MAX
=
t
ON
V
VS CLAMP
=
T
V
R T
source. While the soft start capacitor is charging, and
while V
SS
< (0.4 V
FB)
, the duty cycle, and therefore the
output voltage of the converter is determined by the soft
start circuitry.
At High Line or Low Line fault conditions, the soft start
capacitor is discharged with a controlled discharge cur-
rent of about 500mA. During the discharge time, the duty
cycle of the converter is gradually decreased to zero.
This soft stop feature allows the synchronous rectifiers to
gradually discharge the output LC filter. An abrupt shut
off can cause the LC filter to oscillate, producing unpre-
dictable output voltage levels.
All other fault conditions (UVLO, VREF Low, Over Cur-
rent (0.6V on ILIM) or COUNT) will cause an immediate
stop of the converter. Furthermore, both the Over Current
fault and the COUNT fault will be internally latched until
V
DD
drops below 9V or V
FF
goes below the 600mV
threshold at the input of the Low Line comparator.
After all fault conditions are cleared and the soft start ca-
pacitor is discharged below 200 mV, a soft start cycle will
be initiated to restart the converter.
ILIM:
Provides a pulse by pulse current limit by terminat-
ing the PWM pulse when the input is above 200mV. An
input over 600mV initiates a latched soft stop cycle.
COUNT:
Capacitor to ground integrates current pulses
generated when ILIM exceeds 200mV. A resistor to
ground sets the discharge time constant. A voltage over
4V will initiate a latched soft stop cycle.
FB:
Input to the PWM comparator. This pin is intended
to be driven with an optocoupler circuit. Input impedance
is 50kW Typical modulation range is 1.6V to 3.6V.
SYNC:
Level sensitive oscillator sync input. A high level
forces the gate drive output low and resets the ramp ca-
pacitor. On-time starts at the negative edge the pulse.
There is a 3mA pull down current on the pin, allowing it to
be disconnected when not used.
VREF:
5.0V trimmed reference with 2% variation over
line, load and temperature. Bypass with a minimum of
0.1mF to ground.
SS:
Soft Start pin. A capacitor is connected between this
pin and ground to set the start up time of the converter.
After power up (V
DD
>13V AND V
REF
>4.5V), or after a
fault condition has been cleared, the soft start capacitor
is charged to V
REF
by a nominal 18mA internal current
APPLICATION INFORMATION
(Note: Refer to the Typical Application Diagram on the first
page of this datasheet for external component names.) All the
equations given below should be considered as first order ap-
proximations with final values determined empirically for a spe-
cific application.
Power Sequencing
V
DD
is normally connected through a high impedance
(R6) to the input line, with an additional path (R7) to a
low voltage bootstrap winding on the power transformer.
VFF is connected through a divider (R1/R2) to the input
line.
For circuit activation, all of the following conditions are
required:
1. VFF between 0.6V and 4.0V (operational input voltage
range).
2. VDD has been under the UVLO stop threshold to reset
the shutdown latch.
3. VDD is over the UVLO start threshold.
5
The circuit will start at this point. I
VDD
will increase from
the start up value of 130mA to the run value of 750mA.
The capacitor on SS is charged with a 18mA current.
When the voltage on SS is greater than 0.8V, output
pulses can begin, and supply current will increase to a
level determined by the MOSFET gate charge require-
ments to I
VDD
~ 1mA + QT
·
fs. When the output is ac-
tive, the bootstrap winding should be sourcing the supply
current. If VDD falls below the UVLO stop threshold, the
controller will enter a shutdown sequence and turn the
controller off, returning the start sequence to the initial
condition.
VDD Clamp
An internal shunt regulator clamps VDD so the voltage
does not exceed a nominal value of 14V. If the regulator
is active, supply current must be limited to less than
20mA.
Embedded System
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