ICS8431CM-11LF datasheet, PDF - EEWORLD Datasheet

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ICS8431CM-11LF: DescriptionClock Generator, 255MHz, PDSO28, 7.50 X 18.05, 2.25 MM HEIGHT, SOIC-28; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，18 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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ICS8431CM-11LF Overview

Clock Generator, 255MHz, PDSO28, 7.50 X 18.05, 2.25 MM HEIGHT, SOIC-28

ICS8431CM-11LF Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	SOP,
Contacts	28
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G28
JESD-609 code	e3
length	18.05 mm
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature
Maximum output clock frequency	255 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	20 MHz
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

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Integrated

Circuit

Systems, Inc.

ICS8431-11

255MH

, L

ITTER

, C

RYSTAL

SCILLATOR

-3.3V LVPECL F

REQUENCY

YNTHESIZER

EATURES

•

Fully integrated PLL

•

Differential 3.3V LVPECL output

•

Crystal oscillator interface

•

Output frequency range: 95MHz to 255MHz

•

Crystal input frequency range: 14MHz to 20MHz

•

VCO range: 190MHz to 510MHz

•

Programmable PLL loop divider for generating a variety

of output frequencies

•

Spread Spectrum Clocking (SSC) fixed at 1/2% modulation

for environments requiring ultra low EMI

•

PLL bypass modes supporting in-circuit testing and on-chip

functional block characterization

•

Cycle-to-cycle jitter: 30ps (maximum)

•

3.3V supply voltage

•

0°C to 85°C ambient operating temperature

ENERAL

ESCRIPTION

The ICS8431-11 is a general purpose clock

frequency synthesizer for IA64/32 application and

HiPerClockS™

a member of the HiPerClockS™ family of High

Performance Clock Solutions from ICS. The VCO

operates at a frequency range of 190MHz to

510MHz providing an output frequency range of 95MHz to

255MHz. The output frequency can be programmed using the

parallel interface, M0 thru M8, to the configuration logic.

Spread spectrum clocking is programmed via the control

inputs SSC_CTL0 and SSC_CTL1.

,&6

Programmable features of the ICS8431-11 support four

operational modes. The four modes are spread spectrum

clocking (SSC), non-spread spectrum clock and two test

modes which are controlled by the SSC_CTL[1:0] pins. Un-

like other synthesizers, the ICS8431-11 can immediately

change spread-spectrum operation without having to reset

the device.

In SSC mode, the output clock is modulated in order to

achieve a reduction in EMI. In one of the PLL bypass test

modes, the PLL is disconnected as the source to the

differential output allowing an external source to be

connnected to the TEST_I/O pin. This is useful for in-

circuit testing and allows the differential output to be driven

at a lower frequency throughout the system clock tree. In the

other PLL bypass mode, the oscillator divider is used as the

source to both the M and the Fout divide by 2. This is useful

for characterizing the oscillator and internal dividers.

LOCK

IAGRAM

XTAL1

OSC

XTAL2

SSIGNMENT

SSC_CTL0

SSC_CTL1

TEST_I/O

nP_LOAD

XTAL2

XTAL1

CCA

CCO

FOUT

nFOUT

PHASE

DETECTOR

PLL

VCO

FOUT

nFOUT

ICS8431-11

TEST_I/O

Configuration

Logic

SSC

Control

Logic

M0:M8

28-Lead SOIC

7.5mm x 18.05mm x 2.25mm package body

M Package

Top View

nP_LOAD

8431CM-11

SSC_CTL0

SSC_CTL1

www.icst.com/products/hiperclocks.html

REV. B AUGUST 7, 2002

Integrated

Circuit

Systems, Inc.

UNCTIONAL

ESCRIPTION

ICS8431-11

255MH

, L

ITTER

, C

RYSTAL

SCILLATOR

-3.3V LVPECL F

REQUENCY

YNTHESIZER

The ICS8431-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.

A 16MHz series-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by

16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over

a range of 190MHz to 510MHz. The output of the M divider is also applied to the phase detector.

The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the

VCO is scaled by a divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle.

The programmable features of the ICS8431-11 support four output operational modes and a programmable M divider and

output divider. The four output operational modes are spread spectrum clocking (SSC), non-spread spectrum clock and

two test modes and are controlled by the SSC_CTL[1:0] pins.

The PLL loop divider or M divider is programmed by using inputs M0 through M8. While the nP_LOAD input is held LOW, the

data present at M0:M8 is transparent to the M divider. On the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is latched

into the M divider and any further changes at the M0:M8 inputs will not be seen by the M divider until the next LOW transition

on nP_LOAD.

The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:

fxtal x

The M value and the required values of M0:M8 for programming the VCO are shown in

Table 3B,

Programmable VCO Frequency

Function Table. The frequency out is defined as follows:

fVCO =

FOUT = fVCO = fxtal x M

For the ICS8431-11, the output divider equals 2. Valid M values for which the PLL will achieve lock are defined as 190

≤

510.

8431CM-11

www.icst.com/products/hiperclocks.html

REV. B AUGUST 7, 2002

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