HD74AC112T-ELL datasheet, PDF - EEWORLD Datasheet

HD74AC112T-ELL: DescriptionJ-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TTP-16DA; Categorylogic logic; File Size55KB，8 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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HD74AC112T-ELL Overview

J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TTP-16DA

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Parts packaging code	SOIC
package instruction	TSSOP,
Contacts	16
Reach Compliance Code	unknown
Is Samacsys	N
series	AC
JESD-30 code	R-PDSO-G16
length	5 mm
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	15 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
width	4.4 mm
minfmax	125 MHz
Base Number Matches	1

HD74AC112/HD74ACT112

Dual JK Negative Edge-Triggered Flip-Flop

ADE-205-364 (Z)

1st. Edition

Sep. 2000

Description

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to

each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level

of the J and K inputs may change when the clock is High and the bistable will perform according to the

Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs

on the falling edge of the clock pulse.

Features

•

Outputs Source/Sink 24 mA

•

HD74ACT112 has TTL-Compatible Inputs

Pin Arrangement

GND 8

(Top view)

16 V

12 K

11 J

9 Q

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Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

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