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EDI88512LPA17TI

Description
Standard SRAM, 512KX8, 17ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, DIP-32
Categorystorage    storage   
File Size265KB,9 Pages
ManufacturerWhite Microelectronics
Download Datasheet Parametric View All

EDI88512LPA17TI Overview

Standard SRAM, 512KX8, 17ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, DIP-32

EDI88512LPA17TI Parametric

Parameter NameAttribute value
MakerWhite Microelectronics
package instruction0.400 INCH, SIDE BRAZED, DIP-32
Reach Compliance Codeunknown
Maximum access time17 ns
JESD-30 codeR-CDIP-T32
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal locationDUAL
EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
Access Times of 15, 17, 20, 25, 35, 45, 55ns
Data Retention Function (LPA version)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 512Kx8
Commercial, Industrial and Military Temperature Ranges
32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)
36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)
Single +5V (±10%) Supply Operation
The EDI88512CA is a 4 megabit Monolithic CMOS
Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolu-
tionary standard for the four megabit device. All 32 pin
packages are pin for pin upgrades for the single chip
enable 128K x 8, the EDI88128CS. Pins 1 and 30 be-
come the higher order addresses.
The 36 pin revolutionary pinout also adheres to the
JEDEC standard for the four megabit device. The cen-
ter pin power and ground pins help to reduce noise in
high performance systems. The 36 pin pinout also
allows the user an upgrade path to the future 2Mx8.
A Low Power version with Data Retention
(EDI88512LPA) is also available for battery backed
applications. Military product is available compliant to
Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION
36 P
IN
T
OP
V
IEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P
IN
D
ESCRIPTION
32 P
IN
T
OP
V
IEW
32 V
CC
31 A15
30 A17
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A
-18
I/O
0-7
Data Inputs/Outputs
A
0-18
WE
CS
OE
V
CC
V
SS
NC
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
B
LOCK
D
IAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
-7
WE
CS
OE
Aug. 2002 Rev. 9
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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