The CY7C1034DV33 is a high-performance CMOS static
RAM organized as 256K words by 24 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
To write to the device, enable the chip (CE
1
LOW, CE
2
HIGH
and CE
3
LOW) while forcing the Write Enable (WE) input
LOW.
To read from the device, enable the chip by taking CE
1
LOW
CE
2
HIGH and CE
3
LOW while forcing the Output Enable (OE)
LOW and the Write Enable (WE) HIGH. See the truth table at
the back of this data sheet for a complete description of Read
and Write modes.
The 24 I/O pins (I/O
0
–I/O
23
) are placed in a high-impedance
state when the device is deselected (CE
1
HIGH/CE
2
LOW/CE
3
HIGH) or when the output enable (OE) is HIGH
during a Write operation. (CE
1
LOW, CE
2
HIGH, CE
3
LOW
and WE LOW).
Functional Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
256K x 24
ARRAY
SENSE AMPS
I/O
0
–I/O
23
COLUMN
DECODER
CONTROL LOGIC
CE
1
, CE
2
, CE
3
WE
OE
Selection Guide
–8
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
8
185
25
Unit
ns
mA
mA
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
Cypress Semiconductor Corporation
Document #: 001-08351 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 4, 2006
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PRELIMINARY
Pin Configurations
[1]
119 PBGA
Top View
CY7C1034DV33
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
NC
I/O
12
I/O
13
I/O
14
I/O
15
I/O
16
I/O
17
NC
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
NC
NC
2
A
A
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
A
3
A
A
CE
2
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
NC
A
A
4
A
CE
1
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
WE
OE
5
A
A
CE
3
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
NC
A
A
6
A
A
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
A
7
NC
NC
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
NC
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
NC
NC
Note:
1. NC pins are not connected on the die
Document #: 001-08351 Rev. *A
Page 2 of 8
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
Relative to
GND
[2]
....
–0.5V to +4.6V
Range
Commercial
DC Voltage Applied to Outputs
in High-Z State
[2]
.................................... –0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
CY7C1034DV33
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ............ ...............................>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ..................................................... >200 mA
Operating Range
Ambient
Temperature
0°C to +70°C
V
CC
3.3V
±
0.3V
................................–0.5V to V
CC
+ 0.5V
DC Electrical Characteristics
Over the Operating Range
–8
Parameter
V
OH
V
OL
V
IH
V
IL[2]
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current
Automatic CE Power-down
Current —TTL Inputs
Automatic CE Power-down
Current —CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
V
CC
= Max., f = f
MAX
= 1/t
RC
,
I
OUT
= 0 mA CMOS levels
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V, or V
IN
< 0.3V, f = 0
Test Conditions
[7]
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.3
–1
–1
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
185
30
25
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
8
10
Unit
pF
pF
Thermal Resistance
[3]
Parameter
Θ
JA
Θ
JC
Description
Test Conditions
PBGA
TBD
TBD
Unit
°C/W
°C/W
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms
[4]
50Ω
OUTPUT
Z
0
= 50Ω
V
TH
= 1.5V
30 pF* * Capacitive Load consists of all compo-
nents of the test environment.
3.0V
GND
Rise time > 1 V/ns
ALL INPUT PULSES
90%
10%
90%
10%
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
351Ω
R1 317Ω
(a)
(b)
(c)
Fall time: > 1 V/ns
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). 100
µs
(t
power
) after reaching the minimum
operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
Document #: 001-08351 Rev. *A
Page 3 of 8
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PRELIMINARY
AC Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE active LOW to Write End
[7]
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[8]
WE LOW to High-Z
[8]
8
6
6
0
0
6
5
0
3
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE active LOW to Data Valid
[7]
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8]
CE active LOW to Low-Z
[7, 8]
CE deselect HIGH to High-Z
[7, 8]
CE active LOW to Power-up
[7, 9]
CE deselect HIGH to Power-down
[7, 9]
0
3
1
3
100
8
Description
[5]
CY7C1034DV33
–8
Min.
Max.
Unit
µs
ns
8
8
5
5
5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of the AC test loads, unless specified otherwise.
6. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access is performed.
7. CE refers to a combination of CE
1
, CE
2
, and CE
3
. CE is active LOW when CE
1
is LOW and CE
2
is HIGH and CE
3
is LOW. CE is deselect HIGH when CE
1
is
HIGH or CE
2
is LOW or CE
3
is HIGH
8. t
HZOE
, t
HZCE
, t
HZWE
, and t
LZOE
, t
LZCE
, t
LZWE
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±200
mV from
steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal write time of the memory is defined by the overlap of CE
1
LOW and CE
2
HIGH and CE
3
LOW and WE LOW. The chip enables must be active and
WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced
to the leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 001-08351 Rev. *A
Page 4 of 8
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PRELIMINARY
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[12]
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 2V , CE
1
> V
CC
– 0.2V,
CE
2
< 0.2V, V
IN
> V
CC
– 0.2V or
V
IN
< 0.2V
0
t
RC
Conditions
Min.
2
CY7C1034DV33
Typ.
Max.
25
Unit
V
mA
Chip Deselect to Data Retention Time
Operation Recovery Time
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
3V
t
CDR
CE
V
DR
> 2V
3V
t
R
Switching Waveforms
Read Cycle No. 1
[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[7, 14, 15]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
I
CC
HIGH
IMPEDANCE
Notes:
12. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
µs
or stable at V
CC(min.)
> 50
µs
13. Device is continuously selected. OE, CE = V
IL
.
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
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