EP910IPI-25 datasheet, PDF - EEWORLD Datasheet

EP910IPI-25: DescriptionOT PLD, 28ns, CMOS, PDIP40, PLASTIC, DIP-40; CategoryProgrammable logic devices Programmable logic; File Size200KB，8 Pages; ManufacturerAltera (Intel)

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EP910IPI-25 Overview

OT PLD, 28ns, CMOS, PDIP40, PLASTIC, DIP-40

Parameter Name	Attribute value
Maker	Altera (Intel)
Parts packaging code	DIP
package instruction	DIP,
Contacts	40
Reach Compliance Code	unknown
Other features	MACROCELLS INTERCONNECTED BY GLOBAL BUS; 24 MACROCELLS; 2 EXTERNAL CLOCKS
maximum clock frequency	40 MHz
JESD-30 code	R-PDIP-T40
length	52.425 mm
Dedicated input times	12
Number of I/O lines	24
Number of terminals	40
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	12 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Programmable logic type	OT PLD
propagation delay	28 ns
Certification status	Not Qualified
Maximum seat height	4.83 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm

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