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LP3985
SNVS087AE – OCTOBER 2000 – REVISED MAY 2015
LP3985 Micropower, 150-mA Low-Noise Ultra-Low-Dropout CMOS Voltage Regulator
1 Features
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•
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1
3 Description
The LP3985 is designed for portable and wireless
applications with demanding performance and space
requirements. LP3985 performance is optimized for
battery-powered systems to deliver ultra low noise,
extremely low dropout voltage, and low quiescent
current. Regulator ground current increases only
slightly in dropout, further prolonging the battery life.
The LP3985 is stable with a small 1-µF ±30%
ceramic or high-quality tantalum output capacitor. The
DSBGA requires the smallest possible PC board area
- the total application circuit area can be less than 2
mm x 2.5 mm, a fraction of a 1206 case size.
An optional external bypass capacitor reduces the
output noise without slowing down the load transient
response. Fast startup time is achieved by utilizing an
internal power-on circuit that actively pre-charges the
bypass capacitor.
Power supply rejection is better than 50 dB at low
frequencies and starts to roll off at 1 kHz. High power
supply rejection is maintained down to low input
voltage levels common to battery operated circuits.
The device is ideal for mobile phone and similar
battery-powered wireless applications. It provides up
to 150 mA, from a 2.5-V to 6-V input. The LP3985
consumes less than 1.5 µA in disable mode and has
fast turn-on time less than 200 µs.
The LP3985 is available with fixed output voltages
from 2.5 V to 5 V. Contact Texas Instruments Sales
for specific voltage option needs.
Device Information
(1)
PART
NUMBER
PACKAGE
DSBGA (5)
SOT-23 (5)
BODY SIZE
1.502 mm x 1.045 mm (MAX)
2.90 mm x 1.60 mm (NOM)
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Input Voltage: 2.5 V to 6 V
100-mV Maximum Dropout with 150-mA Load
150-mA Verified Output
50-dB PSRR at 1 kHz at V
IN
= V
OUT
+ 0.2 V
≤
1.5-μA Quiescent Current when Shut Down
Fast Turn-On time: 200
μs
(typ.)
30-μV
RMS
Output Noise (typical) over 10 Hz to 100
kHz
−40°C
to 125°C Junction Temperature Range for
Operation
2.5-V, 2.6-V, 2.7-V, 2.8-V, 2.85-V, 2.9-V, 3-V, 3.1-
V, 3.2-V, 3.3-V, 4.7-V, 4.75-V, 4.8-V and 5-V
Outputs Standard
Logic Controlled Enable
Stable with Ceramic and High-Quality Tantalum
Capacitors
Fast Turnon
Thermal Shutdown and Short-Circuit Current Limit
2 Applications
•
•
•
•
CDMA Cellular Handsets
Wideband CDMA Cellular Handsets
GSM Cellular Handsets
Portable Information Appliances
space
Simplified Schematic
1(C3)
IN
1µF
OUT
1µF
5(C1)
LP3985
LP3985
3(A1)
4(A3)
EN
2(B2)
BYPASS
*
(1) For all available packages, see the Package Option
Addendum at the end of the datasheet.
Pin Numbers in parenthesis indicate DSBGA package.
* Optional Noise Reduction Capacitor.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3985
SNVS087AE – OCTOBER 2000 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Performance Characteristics ........................
1
1
1
2
3
4
4
4
4
4
5
7
7.4 Device Functional Modes........................................
14
8
Application and Implementation
........................
15
8.1 Application Information............................................
15
8.2 Typical Application .................................................
15
9 Power Supply Recommendations......................
18
10 Layout...................................................................
19
10.1
10.2
10.3
10.4
11.1
11.2
11.3
11.4
Layout Guidelines .................................................
Layout Examples...................................................
DSBGA Mounting..................................................
DSBGA Light Sensitivity .......................................
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
21
21
21
21
11 Device and Documentation Support
.................
21
7
Detailed Description
............................................
13
7.1 Overview .................................................................
13
7.2 Functional Block Diagram .......................................
13
7.3 Feature Description.................................................
13
12 Mechanical, Packaging, and Orderable
Information
...........................................................
21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision AD (October 2014) to Revision AE
•
•
•
•
Page
Changed update pin names to TI nomenclature; replace
Handling Ratings
with
ESD Ratings
...........................................
1
Deleted
Voltage Options
table - information in POA .............................................................................................................
1
Added GND as type for ground pins .....................................................................................................................................
3
Added
Thermal Considerations
sub-section ........................................................................................................................
17
Changes from Revision AC (May 2013) to Revision AD
•
Page
Added
Device Information
and
Handling Rating
tables,
Feature Description, Device Functional Modes, Application
and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support,
and
Mechanical, Packaging, and Orderable Information
sections; moved some curves to
Application Curves
section; add
new
Thermal Information........................................................................................................................................................
1
Changes from Revision AB (May 2013) to Revision AC
•
Page
Changed layout of National Data Sheet to TI format ...........................................................................................................
20
2
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LP3985
Copyright © 2000–2015, Texas Instruments Incorporated
LP3985
www.ti.com
SNVS087AE – OCTOBER 2000 – REVISED MAY 2015
5 Pin Configuration and Functions
DBV Package
5 Pin SOT-23
Top View
EN
3
GND
2
IN
1
4
BYPASS
5
OUT
YZR Package
5 Pin DSBGA
Top View
BYPASS
A3
GND
IN
C3
B2
A1
EN
C1
OUT
Pin Functions
PIN
NAME
BYPASS
EN
GND
IN
OUT
(1)
DSBGA
NUMBER
(1)
A3
A1
B2
C3
C1
SOT-23
NUMBER
4
3
2
1
5
TYPE
I/O
I
GND
I
O
DESCRIPTION
Optional bypass capacitor for noise reduction
Enable input logic, enable high
Common ground
Input voltage of the LDO
Output voltage of the LDO
The pin numbering scheme for the DSBGA package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers
were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering
scheme had VEN as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and BYPASS as pin 5.
Copyright © 2000–2015, Texas Instruments Incorporated
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LP3985
SNVS087AE – OCTOBER 2000 – REVISED MAY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
IN, EN
OUT
Junction temperature
Lead temperature
Pad temperature
(4)
(1) (2) (3)
MIN
–0.3
−0.3
MAX
6.5
(V
IN
+ 0.3) < 6.5
150
235
235
UNIT
V
°C
Maximum power dissipation
Storage temperature, T
stg
(1)
(2)
(3)
(4)
(5)
SOT-23
(5)
DSBGA
(5)
364
314
–65
150
mW
°C
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended
Operating Conditions.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to potential at the GND pin.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Additional information on lead temperature and pad temperature can be found in Texas Instruments Application Note AN-1187
Leadless
Leadframe Package (LLP)
(SNOA401).
The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: P
D
= (T
J
-
T
A
)/R
θJA
,where T
J
is the junction temperature, T
A
is the ambient temperature, and R
θJA
is the junction-to-ambient thermal resistance.
The 364-mW rating for SOT23-5 appearing under
Absolute Maximum Ratings
results from substituting the Absolute Maximum junction
temperature, 150°C for T
J
, 70°C for T
A
, and 220°C/W for R
θJA
. More power can be dissipated safely at ambient temperatures below
70°C . Less power can be dissipated safely at ambient temperatures above 70°C. The Absolute Maximum power dissipation can be
increased by 4.5 mW for each degree below 70°C, and it must be derated by 4.5 mW for each degree above 70°C.
6.2 ESD Ratings
VALUE
V
(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
V
±2000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
V
IN
V
EN
I
OUT
T
J
(1)
Supply input voltage
ON/OFF input voltage
Output current
Operating junction temperature
−40
2.5
(1)
MAX
6
V
IN
150
125
UNIT
V
V
mA
°C
0
Recommended minimum V
IN
is the greater of 2.5-V or V
OUT(MAX)
+ rated dropout voltage (max) for operating load current.
6.4 Thermal Information
LP3985
THERMAL METRIC
(1)
R
θJA
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
R
θJC(bot)
(1)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
SOT-23 (DBV)
220
79.8
31.6
3.1
31.1
N/A
DSBGA (YZR)
255
0.8
107.9
0.5
107.9
N/A
°C/W
UNIT
5 PINS
For more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics
application report,
SPRA953.
4
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Copyright © 2000–2015, Texas Instruments Incorporated
LP3985
www.ti.com
SNVS087AE – OCTOBER 2000 – REVISED MAY 2015
6.5 Electrical Characteristics
Unless otherwise specified: V
IN
= V
OUT(nom)
+ 0.5 V, C
IN
= 1
μF,
I
OUT
= 1 mA, C
OUT
= 1
μF,
C
BYPASS
= 0.01
μF.
Minimum (MIN)
and Maximum (MAX) values apply over –40°C
≤
T
J
≤
125°C and typical values are T
A
= 25°C, unless otherwise indicated.
(1) (2)
PARAMETER
Output voltage tolerance
Line regulation error
TEST CONDITIONS
I
OUT
= 1 mA
V
IN
= (V
OUT(nom)
+ 0.5 V) to 6 V,
For 4.7-V to 5-V options
For all other options
(4)
MIN
–2
–3
(3)
TYP
MAX
2
(3)
UNIT
% of
V
OUT(nom)
%/V
%/mA
%/mA
mV
P-P
dB
3
0.19
0.1
0.0025
0.0004
1.5
50
0.005
0.002
ΔV
OUT
–0.19
–0.1
Load regulation error
I
OUT
= 1 mA to 150 mA
LP3985IM5 (SOT23-5)
LP3985 (DSBGA)
V
IN
= V
OUT(nom)
+ 1 V,
I
OUT
= 150 mA (Figure
1)
V
IN
= V
OUT(nom)
+ 0.2 V,
f = 1 kHz,
I
OUT
= 50 mA (Figure
2)
V
IN
= V
OUT(nom)
+ 0.2 V,
ƒ = 10 kHz,
I
OUT
= 50 mA (Figure
2)
V
EN
= 1.4 V, I
OUT
= 0 mA
For 4.7-V to 5-V options
For all other options
Output AC line regulation
PSRR
Power supply rejection ratio
40
dB
100
85
155
140
0.003
0.4
20
45
60
600
300
550
200
30
230
±1
165
150
µA
250
200
1.5
2
35
70
100
mV
mV
mV
mV
mA
mA
µs
µV
RMS
nV/
√Hz
nA
0.4
V
V
I
Q
Quiescent current
V
EN
= 1.4 V, I
OUT
= 0 to 150 mA
For 4.7-V to 5-V options
For all other options
V
EN
= 0.4 V
I
OUT
= 1 mA
I
OUT
= 50 mA
I
OUT
= 100 mA
I
OUT
= 150 mA
Output Grounded
(Steady State)
V
OUT
≥
V
OUT(nom)
– 5%
C
BYPASS
= 0.01 µF
BW = 10 Hz to 100 kHz,
C
OUT
= 1 µF
C
BP
= 0
Dropout voltage
(5)
I
SC
I
OUT(PK)
T
ON
e
n
I
EN
V
IL
V
IH
Short circuit current limit
Peak output current
Turnon time
(6)
Output noise voltage
(7)
Output noise density
Maximum low-level input
voltage at EN
Minimum high-level input
voltage at EN
Thermal shutdown
temperature
Thermal shutdown hysteresis
Maximum input current at EN V
EN
= 0.4 V and V
IN
= 6 V
V
IN
= 2.5 V to 6 V
V
IN
= 2.5 V to 6 V
1.4
TSD
160
20
°C
°C
(1)
(2)
(3)
(4)
(5)
(6)
(7)
All limits are verified. All electrical characteristics having room-temperature limits are tested during production with T
A
= 25°C or
correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are specified by correlating the electrical
characteristics to process and temperature variations and applying statistical process control.
The target output voltage, which is labeled V
OUT(NOM)
, is the desired voltage option.
T
A
= 25°C only.
An increase in the load current results in a slight decrease in the output voltage and vice versa.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification
does not apply for input voltages below 2.5V.
Turnon time is time measured between the enable input just exceeding V
IH
and the output voltage just reaching 95% of its nominal
value.
The output noise varies with output voltage option. The 30 µV
RMS
is measured with 2.5-V voltage option. To calculate an approximated
output noise for other options, use the equation: (30µV
RMS
)(X)/2.5, where X is the voltage option value.
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