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342MPLFT

Description
SOIC-8, Reel
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size247KB,10 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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342MPLFT Overview

SOIC-8, Reel

342MPLFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeSOIC
package instructionSOP, SOP8,.25
Contacts8
Manufacturer packaging codeDCG8
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G8
JESD-609 codee3
length4.9 mm
Humidity sensitivity level1
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency200 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency50 MHz
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage3.45 V
Minimum supply voltage3.15 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
DATASHEET
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER
ICS342
Description
The ICS342 is a low cost, dual-output, field programmable
clock synthesizer. The ICS342 can generate two output
frequencies from 250 kHz to 200 MHz, using up to two
independently configurable PLLs. The outputs may employ
Spread Spectrum techniques to reduce system
electro-magnetic interference (EMI).
Using IDT’s VersaClock
TM
software to configure the PLL
and output, the ICS342 contains a One-Time
Programmable (OTP) ROM to allow field programmability.
Programming features include 2 selectable configuration
registers. Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple crystals
and oscillators, saving board space and cost.
The device also has a power down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS342 is also available in factory programmed custom
versions for high-volume applications.
Features
8-pin SOIC package (Pb-free)
Highly accurate frequency generation
M/N Multiplier PLL: M = 1...2048, N = 1...1024
Output clock frequencies up to 200 MHz
Two ROM locations for frequency and spread selection
Spread spectrum capability for lower system EMI
Center or Down Spread up to 4% total
Selectable 32 kHz or 120 kHz modulation
Input crystal frequency from 5 to 27 MHz
Input clock frequency from 2 to 50 MHz
Operating voltage of 3.3 V
Advanced, low power CMOS process
For one output clock, use the ICS341. For three output
clocks, see the ICS343. For more than three outputs, see
the ICS345 or ICS348.
Block Diagram
VDD
SEL
Crystal or
clock input
X1/ICLK
OTP ROM
with PLL
Divider
Values
CLK1
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
Crystal
Oscillator
X2
External capacitors are
required with a crystal input.
CLK2
GND
PDTS (both outputs and PLL)
IDT® / ICS™
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 1
ICS342
REV N 090613
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