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FEATURES
Micropower: 100 A/DAC
0.1 A Typical Power Shutdown
Single Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP 24-Lead Package
AD7396: 12-Bit Resolution
AD7397: 10-Bit Resolution
0.9 LSB Differential Nonlinearity Error
APPLICATIONS
Automotive Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
LDA
CS
A/B
DATA
12
3 V, Parallel Input
Dual 12-Bit /10-Bit DACs
AD7396/AD7397
FUNCTIONAL BLOCK DIAGRAM
AD7396
DACA
REGISTER
V
DD
12
12-BIT
DACA
V
OUTA
INPUTA
REGISTER
1
INPUTB
REGISTER
12
V
REF
LDB
DACB
REGISTER
12-BIT
DACB
V
OUTB
AGND
DGND
RS
SHDN
GENERAL DESCRIPTION
The AD7396/AD7397 series of dual, 12-bit and 10-bit voltage-
output digital-to-analog converters are designed to operate from
a single +3 V supply. Built using a CBCMOS process, these
monolithic DACs offer the user low cost and ease of use in
single supply +3 V systems. Operation is guaranteed over the
supply voltage range of +2.7 V to +5.5 V, making this device
ideal for battery operated applications.
A 12-bit wide data latch loads with a 45 ns write time allowing
interface to fast processors without wait states. The double
buffered input structure allows the user to load the input
registers one at a time, then a single load strobe tied to both
LDA+LDB
inputs will simultaneously update both DAC out-
puts.
LDA
and
LDB
can also be independently activated to
immediately update their respective DAC registers. An address
input (A/B) decodes DACA or DACB when the chip select
CS
input is strobed. Additionally, an asynchronous
RS
input sets
the output to zero-scale at power on or upon user demand.
Power shutdown to submicroamp levels is directly controlled by
the active low
SHDN
pin. While in the power shutdown state
register data can still be changed even though the output buffer
is in an open circuit state. Upon return to the normal operating
state the latest data loaded in the DAC register will establish the
output voltage.
Both parts are offered in the same pinout, allowing users to
select the amount of resolution appropriate for their applications
without circuit card changes.
The AD7396/AD7397 are specified for operation over the ex-
tended industrial (–40°C to +85°C) temperature range. The
AD7397AR is specified for the –40°C to +125°C automotive
temperature range. AD7396/AD7397s are available in plastic
DIP, and 24-lead SOIC packages. The AD7397ARU is avail-
able for ultracompact applications in a thin 1.1 mm height
TSSOP 24-lead package.
1.0
0.8
0.6
0.4
V
DD
= +3V
V
REF
= +2.5V
DNL – LSB
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
512
1024
1536
2048
2560
CODE – Decimal
3072
3584
4096
T
A
= +25 C, +85 C, –55 C
SUPERIMPOSED
Figure 1. DNL vs. Digital Code at Temperature
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
AD7396/AD7397–SPECIFICATIONS
AD7396 12-BIT
ELECTRICAL CHARACTERISTICS
(@ V
Parameter
STATIC PERFORMANCE
Resolution
1
Relative Accuracy
2
Relative Accuracy
2
Differential Nonlinearity
2
Differential Nonlinearity
2
Zero-Scale Error
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Voltage Error
Full-Scale Tempco
3
REFERENCE INPUT
V
REF
Range
Input Resistance
Input Capacitance
3
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Capacitive Load
3
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
3
INTERFACE TIMING
3, 5
Chip Select Write Width
DAC Select Setup
DAC Select Hold
Data Setup
Data Hold
Load Setup
Load Hold
Load Pulsewidth
Reset Pulsewidth
AC CHARACTERISTICS
Output Slew Rate
Settling Time
6
Shutdown Recovery Time
DAC Glitch
Digital Feedthrough
Feedthrough
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Shutdown Supply Current
Power Dissipation
Power Supply Sensitivity
Symbol
N
INL
INL
DNL
DNL
V
ZSE
V
ZSE
V
FSE
V
FSE
TCV
FS
V
REF
R
REF
C
REF
I
OUT
I
OUT
C
L
V
IL
V
IH
I
IL
C
IL
t
CS
t
AS
t
AH
t
DS
t
DH
t
LS
t
LH
t
LDW
t
RSW
SR
t
S
t
SDR
Q
Q
V
OUT
/V
REF
Data = 000
H
to FFF
H
to 000
H
To
±
0.1% of Full Scale
Code 7FF
H
to 800
H
to 7FF
H
V
REF
= 1.5 V
DC
+1 V p-p
,
Data = 000
H
, f = 100 kHz
DNL <
±
1 LSB
V
IL
= 0 V, No Load
SHDN
= 0, V
IL
= 0 V, No Load
V
IL
= 0 V, No Load
∆V
DD
=
±
5%
Data = 800
H
,
∆V
OUT
= 5 LSB
Data = 800
H
,
∆V
OUT
= 5 LSB
No Oscillation
REF IN
= +2.5 V, –40 C < T
A
< +85 C, unless otherwise noted)
+3 V
12
±
1.75
±
2.0
±
0.9
±
1
4.0
8.0
±
8
±
20
–45
0/V
DD
2.5
5
1
3
100
0.5
V
DD
– 0.6
10
10
45
30
0
30
20
20
10
30
40
0.05
70
90
65
15
–63
2.7/5.5
125/200
0.1/1.5
600
0.006
10% +5 V
12
±
1.75
±
2.0
±
0.9
±
1
4.0
8.0
±
8
±
20
–45
0/V
DD
2.5
5
1
3
100
0.8
4.0
10
10
35
15
0
15
10
20
10
30
30
0.05
60
80
65
15
–63
2.7/5.5
125/200
0.1/1.5
1000
0.006
10% Units
Bits
LSB max
LSB max
LSB max
LSB max
mV max
mV max
mV max
mV max
ppm/°C typ
V min/max
MΩ typ
4
pF typ
mA typ
mA typ
pF typ
V max
V min
µA
max
pF max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
V/µs typ
µs
typ
µs
typ
nV/s typ
nV/s typ
dB typ
V min/max
µA
typ/max
µA
typ/max
µW
max
%/% max
Conditions
T
A
= +25°C
T
A
= –40°C, +85°C
T
A
= +25°C, Monotonic
Monotonic
Data = 000
H
, T
A
= +25°C, +85°C
Data = 000
H
, T
A
= –40°C
T
A
= +25°C, +85°C, Data = FFF
H
T
A
= –40°C, Data = FFF
H
V
DD RANGE
I
DD
I
DD_SD
P
DISS
PSS
NOTES
1
One LSB = V
REF
/4096 V for the 12-bit AD7396.
2
The first two codes (000
H
, 001
H
) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
–2–
REV. 0
AD7396/AD7397
AD7397 10-BIT
ELECTRICAL CHARACTERISTICS
(@ V
Parameter
STATIC PERFORMANCE
Resolution
1
Relative Accuracy
2
Relative Accuracy
2
Differential Nonlinearity
2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Voltage Error
Full-Scale Tempco
3
REFERENCE INPUT
V
REF
Range
Input Resistance
Input Capacitance
3
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Capacitive Load
3
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
3
INTERFACE TIMING
3, 5
Chip Select Write Width
DAC Select Setup
DAC Select Hold
Data Setup
Data Hold
Load Setup
Load Hold
Load Pulsewidth
Reset Pulsewidth
AC CHARACTERISTICS
Output Slew Rate
Settling Time
6
Shutdown Recovery Time
DAC Glitch
Digital Feedthrough
Feedthrough
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Shutdown Supply Current
Power Dissipation
Power Supply Sensitivity
Symbol
N
INL
INL
DNL
V
ZSE
V
FSE
V
FSE
TCV
FS
V
REF
R
REF
C
REF
I
OUT
I
OUT
C
L
V
IL
V
IH
I
IL
C
IL
t
CS
t
AS
t
AH
t
DS
t
DH
t
LS
t
LH
t
LDW
t
RSW
SR
t
S
t
SDR
Q
Q
V
OUT
/V
REF
Data = 000
H
to 3FF
H
to 000
H
To
±
0.1% of Full Scale
Code 7FF
H
to 800
H
to 7FF
H
V
REF
= 1.5 V
DC
+1 V p-p
,
Data = 000
H
, f = 100 kHz
DNL <
±
1 LSB
V
IL
= 0 V, No Load
SHDN
= 0, V
IL
= 0 V, No Load
V
IL
= 0 V, No Load
∆V
DD
=
±
5%
Data = 200
H
,
∆V
OUT
= 5 LSB
Data = 200
H
,
∆V
OUT
= 5 LSB
No Oscillation
REF IN
= +2.5 V, –40 C < T
A
< +85 C, unless otherwise noted)
+3 V
10
±
1.75
±
2.0
±
1
9.0
±
42
±
48
–45
0/V
DD
2.5
5
1
3
100
0.5
V
DD
– 0.6
10
10
45
30
0
30
20
20
10
30
40
0.05
70
90
65
15
–63
2.7/5.5
125/200
0.1/1.5
600
0.006
10% +5 V
10
±
1.75
±
2.0
±
1
9.0
±
42
±
48
–45
0/V
DD
2.5
5
1
3
100
0.8
4.0
10
10
35
15
0
15
10
20
10
30
30
0.05
60
80
65
15
–63
2.7/5.5
125/200
0.1/1.5
1000
0.006
10% Units
Bits
LSB max
LSB max
LSB max
mV max
mV max
mV max
ppm/°C typ
V min/max
MΩ typ
4
pF typ
mA typ
mA typ
pF typ
V max
V min
µA
max
pF max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
V/µs typ
µs
typ
µs
typ
nV/s typ
nV/s typ
dB typ
V min/max
µA
typ/max
µA
typ/max
µW
max
%/% max
Conditions
T
A
= +25°C
T
A
= –40°C, +85°C, +125°C
Monotonic
Data = 000
H
T
A
= +25°C, +85°C, +125°C, Data = 3FF
H
T
A
= –40°C, Data = 3FF
H
V
DD RANGE
I
DD
I
DD_SD
P
DISS
PSS
NOTES
1
One LSB = V
REF
/4096 V for the 10-bit AD7397.
2
The first two codes (000
H
, 001
H
) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
REV. 0
–3–
AD7396/AD7397
t
CSW
CS
t
AS
t
AH
A/B
B REGISTER
t
DS
t
DH
D0–D11
1 OF 12
LATCHES
OF THE 2 INPUT
REGISTERS
t
LS
LDA, LDB
DBx
t
LH
t
RSW
t
LDW
CS
A/B
RS
TO DAC
REGISTERS
RS
t
S
V
OUT
t
S
1 LSB
ERROR BAND
Figure 2. Timing Diagram
Figure 3. Digital Control Logic
Table I. Control Logic Truth
CS
L
L
L
L
H
H
X
H
A/B
L
H
L
H
X
X
X
X
LDA
H
H
H
L
L
^
X
X
LDB
H
H
L
H
L
^
X
X
RS
H
H
H
H
H
H
L
^
SHDN
X
X
X
X
X
X
X
X
Input Register
Write to B
Write to A
Write to B
Write to A
Latched
Latched
Reset to Zero Scale
Latched to Zero
DAC Register
Latched with Previous Data
Latched with Previous Data
B Transparent
A Transparent
A and B Transparent
Latched with New Data from Input REG
Reset to Zero Scale
Latched to Zero
^Denotes positive edge. The
SHDN
pin has no effect on the digital interface data loading; however, while in the
SHDN
state (SHDN = 0) the output amplifiers V
OUTA
and V
OUTB
exhibit an open circuit condition. Note, the
LDx
inputs are level-sensitive, the respective DAC registers are in a transparent state when
LDx
= “0.”
–4–
REV. 0
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