TPS54519
www.ti.com
SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013
2.95 V to 6 V Input, 5-A Synchronous Step Down SWIFT™ Converter
1
FEATURES
•
Two 30 mΩ (typical) MOSFETs for high
efficiency at 5-A loads
200kHz to 2MHz Switching Frequency
0.6 V Voltage Reference With ± 1% Initial
Accuracy
Adjustable Slow Start / Sequencing
UV and OV Power Good Output
Low Operating and Shutdown Quiescent
Current
Safe Start-up into Pre-Biased Output
Cycle by Cycle Current Limit, Thermal and
Frequency Fold Back Protection
–40°C to 140°C Operating Junction
Temperature Range
Thermally Enhanced 3mm × 3mm 16-pin QFN
DESCRIPTION
The TPS54519 device is a full featured 6 V, 5 A,
synchronous step down current mode converter with
two integrated MOSFETs.
The TPS54519 enables small designs by integrating
the MOSFETs, implementing current mode control to
reduce external component count, reducing inductor
size by enabling up to 2 MHz switching frequency,
and minimizing the IC footprint with a small 3mm x
3mm thermally enhanced QFN package.
Efficiency is maximized through the integrated 30mΩ
MOSFETs and 350μA typical supply current. Using
the enable pin, shutdown supply current is reduced to
2
μA
by entering a shutdown mode.
Under voltage lockout is internally set at 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The output
voltage startup ramp is controlled by the slow start
pin. An open drain power good signal indicates the
output is within 93% to 107% of its nominal voltage.
Frequency fold back and thermal shutdown protects
the device during an overcurrent condition.
The TPS54519 is supported in the SwitcherPro™
Software Tool at
www.ti.com/switcherpro.
For more SWIFT™ documentation, see the TI
website at
www.ti.com/swift.
100
2
•
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
Low-Voltage, High-Density Power Systems
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
SIMPLIFIED SCHEMATIC
VIN
VIN
BOOT
CI
R4
TPS54519
EN
R5
PWRGD
VSENSE
SS/TR
RT
COMP
C ss
RT
R3
C1
PH
CO
R1
LO
VOUT
C
BOOT
V
IN
= 5 V
90
Efficiency - %
80
V
IN
= 3 V
70
60
GND
AGND
POWERPAD
R2
50
0
V
OUT
= 1.2 V
F
SW
= 1MHz
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
I
L
- Load Current - A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, SwitcherPro are trademarks of Texas Instruments.
Copyright © 2011–2013, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS54519
SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
T
J
–40°C to 140°C
PACKAGE
3 × 3 mm QFN
PART NUMBER
TPS54519RTE
ABSOLUTE MAXIMUM RATINGS
VALUE
MIN
Input voltage
VIN
EN
BOOT
VSENSE
COMP
PWRGD
SS/TR
RT
Output voltage
BOOT-PH
PH
PH 10 ns Transient
Source current
Sink current
EN
RT
COMP
PWRGD
SS/TR
Electrostatic discharge (HBM)
Electrostatic discharge (CDM)
Operating Junction temperature, T
j
Storage temperature, T
stg
–40
–65
–0.6
–2
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
7
7
PH + 8
3
3
7
3
6
8
7
7
100
100
100
10
100
2
500
140
150
μA
mA
μA
kV
V
°C
°C
μA
V
V
UNIT
THERMAL INFORMATION
THERMAL METRIC
(1) (2)
θ
JA
θ
JA
ψ
JT
ψ
JB
θ
JC(top)
θ
JC(bot)
θ
JB
(1)
(2)
(3)
Junction-to-ambient thermal resistance (standard board)
Junction-to-ambient thermal resistance (custom board)
(3)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(top) thermal resistance
Junction-to-case(bottom) thermal resistance
Junction-to-board thermal resistance
TPS54519
RTE (16 PINS)
49.1
37.0
0.7
21.8
50.7
7.5
21.8
°C/W
UNITS
For more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics
application report,
SPRA953.
Power rating at a specific ambient temperature T
A
should be determined with a junction temperature of 140°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in the application section of this data sheet for more
information.
Test boards conditions:
(a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 4 thermal vias (10mil) located under the device package
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Copyright © 2011–2013, Texas Instruments Incorporated
2
TPS54519
www.ti.com
SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013
ELECTRICAL CHARACTERISTICS
T
J
= –40°C to 140°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal under voltage lockout threshold
Shutdown supply current
Quiescent Current - I
q
ENABLE AND UVLO (EN PIN)
Enable threshold
Input current
VOLTAGE REFERENCE (VSENSE PIN)
Voltage Reference
MOSFET
High side switch resistance
Low side switch resistance
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gm)
Error amplifier transconductance (gm) during
slow start
Error amplifier source/sink
COMP to Iswitch gm
CURRENT LIMIT
Current limit threshold
Low-side reverse current limit
THERMAL SHUTDOWN
Thermal Shutdown
Hysteresis
TIMING RESISTOR (RT PIN)
Switching frequency range using RT mode
Switching frequency
PH (PH PIN)
Minimum On time
Minimum Off time
Rise/Fall Time
Measured at 50% points on PH, VIN = 5 V, IOUT =
500 mA
Prior to skipping off pulses, BOOT-PH = 2.95 V,
IOUT = 4 A
VIN = 5 V
100
60
1.5
ns
ns
V/ns
Rt = 84 kΩ
200
400
490
2000
600
kHz
kHz
150
155
7.5
°C
°C
6.0
7.0
–2.7
8.0
A
A
–2
μA
< I(COMP) < 2
μA,
V(COMP) = 1 V
–2
μA
< I(COMP) < 2
μA,
V(COMP) = 1 V,
Vsense = 0.4 V
V(COMP) = 1 V, 100 mV overdrive
50
250
85
±20
19.0
nA
μmhos
μmhos
μA
A/V
BOOT-PH= 5 V
BOOT-PH= 2.95 V
VIN= 5 V
VIN= 2.95 V
30
35
30
35
60
70
60
70
mΩ
mΩ
0 A
≤
I
OUT
≤
5 A, 25°C
0.594
0.600
0.606
V
Rising
Falling
Enable threshold + 50 mV
Enable threshold – 50 mV
1.16
1.25
1.18
-3.6
-0.7
μA
1.37
V
No voltage hysteresis, rising and falling
EN = 0 V, 25°C, 2.95 V
≤
VIN
≤
6 V
VSENSE = 0.9 V, 25°C, RT = 400 kΩ
2.95
2.4
1
455
6
2.8
5
500
V
V
μA
μA
CONDITIONS
MIN
TYP
MAX
UNIT
Copyright © 2011–2013, Texas Instruments Incorporated
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TPS54519
SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
T
J
= –40°C to 140°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
BOOT (BOOT PIN)
BOOT Charge Resistance
BOOT-PH UVLO
SLOW START / TRACKING (SS/TR PIN)
Charge Current
SS/TR to VSENSE matching
SS to reference crossover
SS discharge voltage (overload)
SS discharge current (UVLO, EN, Thermal
Fault)
POWER GOOD (PWRGD PIN)
VSENSE threshold
Hysteresis
Output high leakage
On resistance
Output low
Minimum VIN for valid output
I(PWRGD) = 3.5 mA
V(PWRGD) < 0.5 V at 100
μA
VSENSE rising (Good)
VSENSE rising (Fault)
VSENSE falling
VSENSE = VREF, V(PWRGD) = 5.5 V
93
110
2
100
78
0.5
0.8
% Vref
% Vref
% Vref
nA
Ω
V
V
V(SS) = 0.3 V
V
SSTR
= 0.3 V
98% nominal
VSENSE = 0 V
VIN = 5 V, V(SS) = 0.5 V
2.4
73
0.87
80
1.2
115
μA
mV
V
μA
mA
VIN = 5 V
VIN = 2.95 V
15
2.1
2.75
Ω
V
CONDITIONS
MIN
TYP
MAX
UNIT
4
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TPS54519
Copyright © 2011–2013, Texas Instruments Incorporated
TPS54519
www.ti.com
SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013
DEVICE INFORMATION
PIN CONFIGURATION
QFN16
RTE Package
(Top View)
PWRGD
BOOT
13
VIN
16
15
EN
14
VIN
1
12
PH
VIN
2
PowerPAD
(17)
11
PH
GND
3
10
PH
GND
4
9
SS/TR
5
6
7
8
VSENSE
AGND
COMP
PIN FUNCTIONS
PIN
NAME
AGND
BOOT
COMP
EN
GND
PH
Thermal
Pad
PWRGD
RT
SS/TR
VIN
VSENSE
NO.
5
13
7
15
3, 4
10, 11, 12
17
14
8
9
1, 2, 16
6
DESCRIPTION
Analog Ground should be electrically connected to GND close to the device.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum
required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
Enable pin, internal pull-up current source. Pull below 1.18 V to disable. Float to enable. Can be used to set the
on/off threshold (adjust UVLO) with two additional resistors.
Power Ground. This pin should be electrically connected directly to the power pad under the IC.
The source of the internal high side power MOSFET, and drain of the internal low side (synchronous) rectifier
MOSFET.
GND pin should be connected to the exposed power pad for proper operation. This thermal pad should be
connected to any internal PCB ground plane using multiple vias for good thermal performance.
An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent, over/under-
voltage or EN shut down.
Resistor Timing.
Slow-start. An external capacitor connected to this pin sets the output voltage rise time. This pin can also be
used for tracking.
Input supply voltage, 2.95 V to 6 V.
Inverting node of the transconductance (gm) error amplifier.
RT
Copyright © 2011–2013, Texas Instruments Incorporated
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