www.ti.com
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017G – JULY 1995 – REVISED SEPTEMBER 2004
FEATURES
•
•
•
•
Member of the Texas Instruments Widebus™
Family
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
DGG OR DL PACKAGE
(TOP VIEW)
DESCRIPTION/ORDERING INFORMATION
This 12-bit to 24-bit bus exchanger is designed for
1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16271 is intended for applications in
which two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. This
device is particularly suitable as an interface
between conventional DRAMs and high-speed
microprocessors.
A data is stored in the internal A-to-B registers on the
low-to-high transition of the clock (CLK) input,
provided that the clock-enable (CLKENA) inputs are
low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit
word on the B port.
Transparent latches in the B-to-A path allow
asynchronous operation to maximize memory access
throughput. These latches transfer data when the
latch-enable (LE) inputs are low. The select (SEL)
line selects 1B or 2B data for the A outputs. Data flow
is controlled by the active-low output enables (OEA,
OEB).
line
OEA
LE1B
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
LE2B
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEB
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
space
To ensure the high-impedance state during power up or power down, the output enables should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
T
A
SSOP - DL
TSSOP - DGG
(1)
PACKAGE
(1)
Tube
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
SN74ALVCH16271DL
SN74ALVCH16271DLR
TOP-SIDE
MARKING
ALVCH16271
-40°C to 85°C
SN74ALVCH16271DGGR ALVCH16271
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017G – JULY 1995 – REVISED SEPTEMBER 2004
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage range
Output voltage range
(2) (3)
Input clamp current
Output clamp current
Continuous output current
Continuous current through each V
CC
or GND
θ
JA
T
stg
(1)
(2)
(3)
(4)
Package thermal impedance
(4)
Storage temperature range
DGG package
DL package
-65
V
I
< 0
V
O
< 0
Except I/O
ports
(2)
I/O ports
(2) (3)
-0.5
-0.5
-0.5
-0.5
MAX
4.6
4.6
V
CC
+ 0.5
V
CC
+ 0.5
-50
-50
±50
±100
64
56
150
UNIT
V
V
V
mA
mA
mA
mA
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
V
CC
V
IH
Supply voltage
V
CC
= 1.65 V to 1.95 V
High-level input voltage
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 1.65 V to 1.95 V
V
IL
V
I
V
O
Low-level input voltage
Input voltage
Output voltage
V
CC
= 1.65 V
I
OH
High-level output current
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3 V
V
CC
= 1.65 V
I
OL
Low-level output current
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3 V
∆t/∆v
T
A
(1)
Input transition rise or fall rate
Operating free-air temperature
-40
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
0
0
1.65
0.65
×
V
CC
1.7
2
0.35
×
V
CC
0.7
0.8
V
CC
V
CC
-4
-12
-12
-24
4
12
12
24
10
85
ns/V
°C
mA
mA
V
V
V
V
MAX
3.6
UNIT
V
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
4
www.ti.com
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017G – JULY 1995 – REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
I
OH
= -100
µA
I
OH
= -4 mA
I
OH
= -6 mA
V
OH
I
OH
= -12 mA
I
OH
= -24 mA
I
OL
= 100
µA
I
OL
= 4 mA
V
OL
I
OL
= 6 mA
I
OL
= 12 mA
I
OL
= 24 mA
I
I
V
I
= V
CC
or GND
V
I
= 0.58 V
V
I
= 1.07 V
V
I
= 0.7 V
I
I(hold)
V
I
= 1.7 V
V
I
= 0.8 V
V
I
= 2 V
V
I
= 0 to 3.6
I
OZ (3)
I
CC
∆I
CC
C
i
C
io
(1)
(2)
(3)
Control inputs
A or B ports
V
(2)
I
O
= 0
Other inputs at V
CC
or GND
V
O
= V
CC
or GND
V
I
= V
CC
or GND,
One input at V
CC
- 0.6 V,
V
I
= V
CC
or GND
V
O
= V
CC
or GND
TEST CONDITIONS
V
CC
1.65 V to 3.6 V
1.65 V
2.3 V
2.3 V
2.7 V
3V
3V
1.65 V to 3.6 V
1.65 V
2.3 V
2.3 V
2.7 V
3V
3.6 V
1.65 V
1.65 V
2.3 V
2.3 V
3V
3V
3.6 V
3.6 V
3.6 V
3 V to 3.6 V
3.3 V
3.3 V
3.5
9
25
-25
45
-45
75
-75
±500
±10
40
750
µA
µA
µA
pF
pF
µA
MIN TYP
(1)
V
CC
- 0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
±5
µA
V
V
MAX
UNIT
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter I
OZ
includes the input leakage current.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
V
CC
= 2.5 V
±
0.2 V
MIN
f
clock
t
w
t
su
Clock frequency
Pulse duration, CLK high or low
A before CLK↑
Setup time
B before LE
CLKEN before CLK↑
A after CLK↑
t
h
Hold time
B after LE
CLKEN after CLK↑
3.3
2.6
1.7
1.6
0.6
0.9
1
MAX
130
3.3
2.1
1.5
1.3
0.6
0.9
0.9
V
CC
= 2.7 V
MIN
MAX
130
3.3
1.7
1.3
1
0.7
1.1
0.9
ns
ns
V
CC
= 3.3 V
±
0.3 V
MIN
MAX
130
MHz
ns
UNIT
5
京公网安备 11010802033920号
EEWORLD
