PI6CVF857ZD datasheet, PDF - EEWORLD Datasheet

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PI6CVF857ZD: DescriptionPLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), TQFN-40; Categorylogic logic; File Size299KB，14 Pages; ManufacturerPericom Semiconductor Corporation (Diodes Incorporated); Websitehttps://www.diodes.com/

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PI6CVF857ZD Overview

PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), TQFN-40

PI6CVF857ZD Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging code	QFN
package instruction	HVQCCN, LCC40,.24SQ,20
Contacts	40
Reach Compliance Code	compliant
ECCN code	EAR99
series	6C
Input adjustment	DIFFERENTIAL
JESD-30 code	S-XQCC-N40
JESD-609 code	e0
length	6 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.012 A
Number of functions	1
Number of inverted outputs
Number of terminals	40
Actual output times	10
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC40,.24SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	235
power supply	2.5 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	6 mm
minfmax	170 MHz

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PI6CVF857

1:10 PLL Clock Driver for

2.5V DDR-SDRAM Memory

Product Features

• Operating Frequency up to 220 MHz for PC3200 Registered

DIMM applications

• Distributes one differential clock input pair to ten differential

clock output pairs

• Inputs (CLK,CLK) and (FBIN,FBIN)

• Input PWRDWN: LVCMOS

• Outputs (Yx, Yx), (FBOUT, FBOUT)

• External feedback pins (FBIN,FBIN) are used to

synchronize the outputs to the clock input

• Operates at 2.5V for PC1600, PC2100, PC2700,

and 2.6V for PC3200

• Packaging (Pb-free & Green available, select packages):

– 48-pin TSSOP

– 40-pin TQFN

– 56-ball VFBGA

Product Description

PI6CVF857 PLL clock device is developed for registered DDR DIMM

applications. The device is a zero-delay buffer that distributes a

differential clock input pair (CLK, CLK) to ten differential pairs of

clock outputs (Y[0:9], Y[0:9]), and one differential pair feedback clock

outputs (FBOUT,FBOUT) . The clock outputs are controlled by the

input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V

LVCMOS input (PWRDWN), and the Analog Power input (AV

When input PWRDWN is low while power is applied, the input

receivers are disabled, the PLL is turned off, and the differential clock

outputs are 3-stated. When the AV

is strapped low, the PLL is

turned off and bypassed for test purposes.

When the input frequency falls below a suggested detection fre-

quency that is below the operating frequency of the PLL, the device

will enter a low power mode. An input frequency detection circuit will

detect the low frequency condition and perform the same low power

features as when the PWRDWN input is low.

The PLL in the PI6CVF857 clock driver uses the input clocks (CLK,

CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor-

mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]).

The PI6CVF857 is also able to track Spread Spectrum Clocking for

reduced EMI.

Block Diagram

FBOUT

CLK

FBIN

PLL

PWRDWN

AVDD

Powerdown

and Test

Logic

PS8683B

10/17/03

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