EP910IDI-15 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> EP910IDI-15

EP910IDI-15: DescriptionUV PLD, 18ns, PAL-Type, CMOS, CDIP40, WINDOWED, CERDIP-40; CategoryProgrammable logic devices Programmable logic; File Size285KB，42 Pages; ManufacturerAltera (Intel)

Download Datasheet Parametric View All

EP910IDI-15 Overview

UV PLD, 18ns, PAL-Type, CMOS, CDIP40, WINDOWED, CERDIP-40

EP910IDI-15 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	DIP
package instruction	WDIP, DIP40,.6
Contacts	40
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	MACROCELLS INTERCONNECTED BY GLOBAL BUS; 24 MACROCELLS; 2 EXTERNAL CLOCKS
Architecture	PAL-TYPE
maximum clock frequency	66.6 MHz
JESD-30 code	R-GDIP-T40
JESD-609 code	e0
length	52.07 mm
Dedicated input times	12
Number of I/O lines	24
Number of entries	36
Output times	24
Number of product terms	450
Number of terminals	40
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	12 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	WDIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE, WINDOW
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	UV PLD
propagation delay	18 ns
Certification status	Not Qualified
Maximum seat height	5.75 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

Preview

Download Datasheet

View All

Classic

EPLD Family

Data Sheet

May 1999, ver. 5

Features

Complete device family with logic densities of 300 to 900 usable gates

(see

Table 1)

Device erasure and reprogramming with non-volatile EPROM

configuration elements

Fast pin-to-pin logic delays as low as 10 ns and counter frequencies

as high as 100 MHz

24 to 68 pins available in dual in-line package (DIP), plastic J-lead

chip carrier (PLCC), pin-grid array (PGA), and small-outline

integrated circuit (SOIC) packages

Programmable security bit for protection of proprietary designs

100% generically tested to provide 100% programming yield

Programmable registers providing D, T, JK, and SR flipflops with

individual clear and clock controls

Software design support featuring the Altera

MAX+PLUS

development system on Windows-based PCs, as well as

Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000

workstations, and third-party development systems

Programming support with Altera’s Master Programming Unit

(MPU); programming hardware from Data I/O, BP Microsystems,

and other third-party programming vendors

Additional design entry and simulation support provided by EDIF,

library of parameterized modules (LPM), Verilog HDL, VHDL, and

other interfaces to popular EDA tools from manufacturers such as

Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,

Synplicity, and VeriBest

Table 1. Classic Device Features

Feature

Usable gates

Macrocells

Maximum user I/O pins

(ns)

CNT

(MHz)

EP610

EP610I

300

100

EP910

EP910I

450

76.9

EP1810

900

Altera Corporation

A-DS-CLASSIC-05

745

Recommended Resources

STK-W-3 microcomputer controller peripheral circuit

LT1220 high-speed operational amplifier circuit

Electronic combination lock 2

555 carrier signal processing and control circuit

Low frequency amplifier circuit with tone and volume adjustment

Computer motherboard circuit diagram 820 2_19

Two small questions, scattered ~: 1. Use the hardware timer to write a program, set the hour, minute and second timers, the corresponding addresses are: 4000H, 4002H, 4004H, the crystal frequency is 12MHZ (written with 8096) 2.C08__2 ...; zhanqianwen Embedded System

[FPGA entry to actual combat] Xilinx ise development tool generates FIFO ip simulation and timing explanation source code & Q&A: [FPGA entry to actual combat] Xilinx ise development tool generates FIFO ip simulation and timing explanation; Students who do not understand the knowledge points in the video can ask questions in the...; 尤老师 FPGA/CPLD

Implementation of Satellite Communication in Windows CE System.pdf: Implementation of Satellite Communication in Windows CE System.pdf...; yuandayuan6999 MCU

Discussion about EDA learning, questions, and advanced: This section seems to be the most active, so I post it here. If there is any violation, please delete or transfer it. I have been doing pure layout design for 3 years. I have encountered many problems...; tiny丨Y PCB Design

Clock output of TMS320F28335: [i=s]This post was last edited by Aguilera on 2017-9-17 22:09[/i] [b][size=4][color=#000000][backcolor=white]1. Clock system[/backcolor][/color][/size][/b][p=35, null, left][size=4][color=#000000][bac...; Aguilera Microcontroller MCU

Understanding of 51 MCU P1 port driving capability: In the 51 single-chip microcomputer series, there are many manufacturers and compatible models. The driving capabilities of the P1 port of single-chip microcomputers produced by different manufacturer...; youki12345 51mcu

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components