CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For
JC
, the “case temp” location is taken at the package top center.
DC Electrical Specifications
Unless otherwise noted, V
DD
= +2.7V to +5.5V, T
A
= -40°C to +85°C, Typical values are @ T
A
= +25°C
and V
DD
= 3.3V.
MIN
(Note 16)
2.7
1.8
MAX
(Note 16)
5.5
5.5
SYMBOL
V
DD
V
BAT
PARAMETER
Main Power Supply
Backup Power Supply
CONDITIONS
TYP
UNIT
V
V
NOTES
Electrical Specifications
SYMBOL
I
DD1
PARAMETER
Supply Current with I
2
C Active
CONDITIONS
V
DD
= 2.7V
V
DD
= 5.5V
I
DD2
Supply Current for Non-Volatile
Programming
Supply Current for Main
Timekeeping (Low Power Mode)
Battery Supply Current
V
DD
= 2.7V
V
DD
= 5.5V
V
DD
= V
SDA
= V
SCL
= 2.7V
V
DD
= V
SDA
= V
SCL
= 5.5V
V
BAT
= 1.8V,
V
DD
= V
SDA
= V
SCL
= V
RESET
= 0
V
BAT
= 3.0V,
V
DD
= V
SDA
= V
SCL
= V
RESET
= 0
I
BATLKG
V
TRIP
V
TRIPHYS
V
BATHYS
V
DD SR-
IRQ/F
OUT
V
OL
Output Low Voltage
V
DD
= 5V
I
OL
= 3mA
V
DD
= 1.8V
I
OL
= 1mA
I
LO
Output Leakage Current
V
DD
= 5.5V
V
OUT
= 5.5V
100
0.4
0.4
400
V
V
nA
Battery Input Leakage
V
BAT
Mode Threshold
V
TRIP
Hysteresis
V
BAT
Hysteresis
V
DD
Negative Slew Rate
V
DD
= 5.5V, V
BAT
= 1.8V
1.8
2.2
30
50
10
800
850
MIN
(Note 16)
TYP
MAX
(Note 16)
500
800
2.5
3.5
10
20
1000
1200
100
2.6
UNIT
µA
µA
mA
mA
µA
µA
nA
nA
nA
V
mV
mV
V/ms
11
11, 14
11, 14
12
7, 10, 11
9
7, 8, 9
NOTES
7, 8, 9
I
DD3
I
BAT
FN8231 Rev 9.00
November 30, 2010
Page 3 of 24
ISL12026, ISL12026A
EEPROM Specifications
PARAMETER
EEPROM Endurance
EEPROM Retention
Temperature
75°C
TEST CONDITIONS
MIN
(Note 16)
>2,000,000
50
TYP
MAX
(Note 16)
UNITS
Cycles
Years
NOTES
Serial Interface (I
2
C) Specifications
DC Electrical Specifications
SYMBOL
V
IL
V
IH
PARAMETER
SDA and SCL Input Buffer LOW
Voltage
SDA and SCL Input Buffer HIGH
Voltage
TEST CONDITIONS
MIN
(Note 16)
-0.3
0.7 x V
DD
0.05 x V
DD
I
OL
= 4mA
V
IN
= 5.5V
V
IN
= 5.5V
0
100
100
0.4
TYP
MAX
(Note 16)
0.3xV
DD
V
DD
+ 0.3
UNITS
V
V
V
V
nA
nA
NOTES
Hysteresis SDA and SCL Input Buffer
Hysteresis
V
OL
I
LI
I
LO
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
AC Electrical Specifications
SYMBOL
f
SCL
t
IN
t
AA
PARAMETER
SCL Frequency
Pulse width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Any pulse narrower than the max
spec is suppressed.
SCL falling edge crossing 30% of
V
DD
, until SDA exits the 30% to 70%
of V
DD
window.
SDA crossing 70% of V
DD
during a
STOP condition, to SDA crossing
70% of V
DD
during the following
START condition.
Measured at the 30% of V
DD
crossing.
Measured at the 70% of V
DD
crossing.
SCL rising edge to SDA falling edge.
Both crossing 70% of V
DD
.
From SDA falling edge crossing
30% of V
DD
to SCL falling edge
crossing 70% of V
DD
.
From SDA exiting the 30% to 70% of
V
DD
window, to SCL rising edge
crossing 30% of V
DD
.
From SCL rising edge crossing 70%
of V
DD
to SDA entering the 30% to
70% of V
DD
window.
1300
TEST CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
400
50
900
UNITS
kHz
ns
ns
NOTES
t
BUF
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
START Condition Hold Time
1300
600
600
600
ns
ns
ns
ns
t
SU:DAT
Input Data Set-up Time
100
ns
t
HD:DAT
Input Data Hold Time
0
ns
FN8231 Rev 9.00
November 30, 2010
Page 4 of 24
ISL12026, ISL12026A
AC Electrical Specifications
SYMBOL
t
SU:STO
PARAMETER
STOP Condition Set-up Time
(Continued)
TEST CONDITIONS
From SCL rising edge crossing 70%
of V
DD
, to SDA rising edge crossing
30% of V
DD
.
From SDA rising edge to SCL falling
edge. Both crossing 70% of V
DD
.
From SCL falling edge crossing 30%
of V
DD
, until SDA enters the 30% to
70% of V
DD
window.
MIN
(Note 16)
600
TYP
MAX
(Note 16)
UNITS
ns
NOTES
t
HD:STO
t
DH
STOP Condition Hold Time for
Read or Volatile Only Write
Output Data Hold Time
600
0
ns
ns
Cpin
t
WC
t
R
t
F
Cb
R
PU
SDA and SCL Pin Capacitance
Non-volatile Write Cycle Time
SDA and SCL Rise Time
SDA and SCL Fall Time
From 30% to 70% of V
DD
From 70% to 30% of V
DD
20 + 0.1xCb
20 +0.1xCb
10
1
12
10
20
300
300
400
pF
ms
ns
ns
pF
k
15
15
15
14
Capacitive Loading of SDA or SCL Total on-chip and off-chip
SDA and SCL Bus Pull-up Resistor Maximum is determined by t
R
and t
F
.
Off-chip
For Cb = 400pF, max is about
2k~2.5k.
For Cb = 40pF, max is about
15k~20k
NOTES:
7. IRQ/F
OUT
Inactive.
8. V
IL
= V
DD
x 0.1, V
IH
= V
DD
x 0.9, f
SCL
= 400kHz
9. V
DD
> V
BAT
+V
BATHYS
10. Bit BSW = 0 (Standard Mode), ATR = 00h, V
BAT
1.8V
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
13. Parameter is not 100% tested.
14. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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