Three chip enables for depth expansion and address
pipeline
Address, control, input, and output pipeline registers
Internally self-timed Write Cycle
Write pass-through capability
Burst control pins (interleaved or linear burst se-
quence)
Automatic power-down for portable applications
High-density, high-speed packages
Low capacitive bus loading
High 30-pF output drive capability at rated access time
The CY7C1298A/GVT7164C18 SRAM integrates 65536x18
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a posi-
tive-edge-triggered Clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), burst control inputs (ADSC, ADSP, and ADV), Write En-
ables (WEL, WEH, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the burst advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. WEL con-
trols DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and
DQP2. WEL and WEH can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. This de-
vice also incorporates Write pass-through capability and pipe-
lined enable circuit for better system performance.
The CY7C1298A/GVT7164C18 operates from a +3.3V power
supply. All inputs and outputs are TTL-compatible. The device
is ideally suited for 486, Pentium®, 680x0, and PowerPC™
systems and for systems that are benefited from a wide syn-
chronous data bus.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced dou-
ble-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
Selection Guide
7C1298A-100
7164C18-5
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
5
360
2
7C1298A-83
7164C18-6
6
315
2
7C1298A-66
7164C18-7
7
270
2
7C1298A-50
7164C18-8
8
225
2
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of International Business Machines, Inc.
Cypress Semiconductor Corporation
Document #: 38-05194 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 19, 2003
CY7C1298A/
GVT7164C18
Functional Block Diagram—64K x 18
[1]
WEH#
* BWE#
UPPER BYTE
WRITE
D
Q
WEL#
* GW#
CE#
* CE2
* CE2#
ZZ
OE#
ADSP#
Power Down Logic
LOWER BYTE
WRITE
D
Q
lo byte write
hi byte write
Output Buffers
ENABLE
D
Q
D
Q
Input
Register
A15-A2
ADSC#
Address
Register
64K x 9 x 2
SRAM Array
OUTPUT
REGISTER
CLR
ADV#
A1-A0
* MODE
Binary
Counter
& Logic
D
Q
DQ1-
DQ16,
DQP1,
DQP2
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05194 Rev. *A
Page 2 of 12
CY7C1298A/
GVT7164C18
Pin Configuration
100-Pin TQFP
Top View
A6
A7
CE
CE2
NC
NC
WEH
WEL
CE2
V
CC
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
NC
NC
V
CCQ
V
SSQ
NC
NC
DQ9
DQ10
V
SSQ
V
CCQ
DQ11
DQ12
V
CC
V
CC
NC
V
SS
DQ13
DQ14
V
CCQ
V
SSQ
DQ15
DQ16
DQP2
NC
V
SSQ
V
CCQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1298A/GVT7164C18
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
NC
NC
V
CCQ
V
SSQ
NC
DQP1
DQ8
DQ7
V
SSQ
V
CCQ
DQ6
DQ5
V
SS
NC
V
CC
ZZ
DQ4
DQ3
V
CCQ
V
SSQ
DQ2
DQ1
NC
NC
V
SSQ
V
CCQ
NC
NC
NC
Pin Descriptions
QFP Pins
37, 36, 35, 34, 33, 32,
100, 99, 82, 81, 80,
48, 47, 46, 45, 44
93, 94
Pin Name
A0–A15
Type
Description
Input-
Addresses: These inputs are registered and must meet the set-up and hold
Synchronous times around the rising edge of CLK. The burst counter generates internal
addresses associated with A0 and A1, during burst cycle and wait cycle.
Input-
Byte Write Enables: A byte write enable is LOW for a Write cycle and HIGH
Synchronous for a Read cycle. WEL controls DQ1–DQ8 and DQP1. WEH controls
DQ9–DQ16 and DQP2. Data I/O are high-impedance if either of these in-
puts are LOW, conditioned by BWE being LOW.
Input-
Write Enable: This active LOW input gates byte write operations and must
Synchronous meet the set-up and hold times around the rising edge of CLK.
Input-
Global Write: This active LOW input allows a full 18-bit Write to occur inde-
Synchronous pendent of the BWE and WEn lines and must meet the set-up and hold
times around the rising edge of CLK.
Input-
Clock: This signal registers the addresses, data, chip enables, write control
Synchronous and burst control inputs on its rising edge. All synchronous inputs must meet
set-up and hold times around the clock’s rising edge.
Input-
Chip Enable: This active LOW input is used to enable the device and to gate
Synchronous ADSP.
Input-
Chip Enable: This active LOW input is used to enable the device.
Synchronous
Input-
Chip Enable: This active HIGH input is used to enable the device.
Synchronous
Page 3 of 12
WEL, WEH
87
88
BWE
GW
89
CLK
98
92
97
CE
CE2
CE2
Document #: 38-05194 Rev. *A
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
CC
NC
NC
A15
A14
A13
A12
A11
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CY7C1298A/
GVT7164C18
Pin Descriptions
(continued)
QFP Pins
86
83
84
Pin Name
OE
ADV
ADSP
Type
Input
Description
Output Enable: This active LOW asynchronous input enables the data out-
put drivers.
Input-
Address Advance: This active LOW input is used to control the internal burst
Synchronous counter. A HIGH on this pin generates wait cycle (no address advance).
Input-
Address Status Processor: This active LOW input, along with CE being
Synchronous LOW, causes a new external address to be registered and a Read cycle is
initiated using the new address.
Input-
Address Status Controller: This active LOW input causes device to be de-
Synchronous selected or selected along with new external address to be registered. A
Read or Write cycle is initiated depending upon write control inputs.
Input-
Static
Input-
Static
Input/
Output
Input/
Output
Supply
Ground
I/O Supply
I/O Ground
-
Mode: This input selects the burst sequence. A LOW on this pin selects
Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
Snooze: LOW or NC for normal operation. HIGH for low-power standby.
Data Inputs/Outputs: Low Byte is DQ1–DQ8. HIgh Byte is DQ9–DQ16.
Input data must meet set-up and hold times around the rising edge of CLK.
Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity
bit for DQ9–DQ16.
Power Supply: +3.3V –5% and +10%.
Ground: GND.
Output Buffer Supply: +3.3V –5% and +10%.
Output Buffer Ground: GND.
No Connect: These signals are not internally connected.
85
ADSC
31
64
MODE
ZZ
58, 59, 62, 63, 68, 69, DQ1–DQ16
72, 73, 8, 9, 12, 13,
18, 19, 22, 23
74, 24
14, 15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
71, 76
1–3, 6, 7, 16, 25,
28–30, 38, 39, 42, 43,
49–53, 56, 57, 66, 75,
78–79, 95, 96
DQP1,
DQP2
V
CC
V
SS
V
CCQ
V
SSQ
NC
Burst Address Table (MODE = NC/V
CC
)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A00
A...A11
A...A10
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Partial Truth Table for Read/Write
Function
READ
READ
WRITE one byte
WRITE all bytes
WRITE all bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
WEH
X
H
L
L
X
WEL
X
H
H
L
X
Document #: 38-05194 Rev. *A
Page 4 of 12
CY7C1298A/
GVT7164C18
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
H
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2 CE2 ADSP
X
X
H
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC
L
X
X
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Pass-Through Truth Table
Previous Cycle
[9]
Operation
Initiate WRITE cycle, all bytes
Address = A(n–1), data = D(n–1)
Initiate WRITE cycle, all bytes
Address = A(n–1), data = D(n–1)
Initiate WRITE cycle, all bytes
Address = A(n–1), data = D(n–1)
Initiate WRITE cycle, one byte
Address = A(n–1), data = D(n–1)
BWn
All L
[10, 11]
All L
[10, 11]
All L
[10, 11]
One L
[10]
Operation
Initiate READ cycle
Register A(n), Q = D(n–1)
No new cycle
Q = D(n–1)
No new cycle
Q = High-Z
No new cycle
Q = D(n–1) for one byte
Present Cycle
CE
L
H
H
H
BWn
H
H
H
H
OE
L
L
H
L
Next Cycle
Operation
Read D(n)
No carry-over from
previous cycle
No carry-over from
previous cycle
No carry-over from
previous cycle
Notes:
2. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE +
WEL*WEH]*GW equals HIGH.
3. WEL enables write to DQ1–DQ8 and DQP1. WEH enables write to DQ9–DQ16 and DQP2.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5. Suspending burst generates wait cycle.
6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
9. Previous cycle may be any cycle (non-burst, burst, or wait).
10. BWE is LOW for individual byte WRITE.
11. GW LOW yields the same result for all-byte WRITE operation.
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