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HM62W1400HTT-12

Description
Cache SRAM, 4MX1, 12ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32
Categorystorage    storage   
File Size336KB,15 Pages
ManufacturerHitachi (Renesas )
Websitehttp://www.renesas.com/eng/
Download Datasheet Parametric View All

HM62W1400HTT-12 Overview

Cache SRAM, 4MX1, 12ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32

HM62W1400HTT-12 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerHitachi (Renesas )
Parts packaging codeTSOP2
package instructionTSOP2, TSOP32,.46
Contacts32
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time12 ns
I/O typeSEPARATE
JESD-30 codeR-PDSO-G32
JESD-609 codee0
length20.95 mm
memory density4194304 bit
Memory IC TypeCACHE SRAM
memory width1
Number of functions1
Number of terminals32
word count4194304 words
character code4000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX1
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP32,.46
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.005 A
Minimum standby current3 V
Maximum slew rate0.18 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width10.16 mm
HM62W1400H Series
4M High Speed SRAM (4-Mword
×
1-bit)
ADE-203-773E (Z)
Rev. 2.0
Nov. 11, 1998
Description
The HM62W1400H is a 4-Mbit high speed static RAM organized 4-Mword
×
1-bit. It has realized high
speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed
circuit designing technology. It is most appropriate for the application which requires high speed and high
density memory, such as cache and buffer memory in system. The HM62W1400H is packaged in 400-mil
32-pin SOJ and 400-mil 32-pin TSOP II for high density surface mounting.
Features
Single 3.3 V supply : 3.3 V
±
0.3 V
Access time 12/15 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current: 180/160 mA (max)
TTL standby current: 60/50 mA (max)
CMOS standby current: 5 mA (max)
: 1 mA (max) (L-version)
Data retension current: 0.6 mA (max) (L-version)
Data retension voltage: 2 V (min) (L-version)
Center V
CC
and V
SS
type pinout
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