530AC808M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530AC808M000DGR

530AC808M000DGR: DescriptionLVPECL Output Clock Oscillator, 808MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530AC808M000DGR Overview

LVPECL Output Clock Oscillator, 808MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530AC808M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Reach Compliance Code	unknow
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	808 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Meiyi brand air curtain type automatic monitoring range hood circuit diagram

Circuit diagram b of the connection methods of some terminals of M62213FP

MC3367 Monolithic FM Radio

Luminous and sound probe circuit

555 power saving, anti-theft automatic lighting circuit

Accurate reference clock oscillator circuit

2017 Fifth IPC China PCB Design Competition Finals - PCB Design Seminar: [url]http://www.ipc.org.cn/events/pcb-design-seminar/2017/index.html[/url] Interested friends can sign up for technical exchanges and learn to improve high-speed PCB design technology together. The qu...; 卢永利 PCB Design

Please help me analyze my circuit.: Hello everyone, I hope you can help me analyze my circuit and answer my questions for a year. Thank you. I am making a signal conditioning circuit with an input signal of 0.1mVp-p and a frequency of 1...; hugx Analogue and Mixed Signal

How to treat obsessive compulsive disorder.: Listing some obsessive-compulsive things, I think I am seriously ill. 1) The board we made uses an A8 processor. When it starts, the serial port will output three A's and a line feed. This part is act...; cl17726 Talking

Link error occurs when compiling project files: Begging for a solution...; 猪头哥哥 DSP and ARM Processors

[Campus Recruitment/Social Recruitment] [Institute of Software, Chinese Academy of Sciences] Image Processing Algorithm Engineer: [i=s]This post was last edited by ninglu on 2017-9-27 18:07[/i] [align=left][align=left]Due to work needs, we plan to recruit a number of scientific researchers, with preferential treatment. They shou...; ninglu Recruitment

Is this a website bug?? or a feature??: As shown in the forum homepage, the left navigation section should normally have 6 recent posts with pictures. When you move the mouse over the numbers, it will switch to the corresponding pictures. C...; wsmysyn Suggestions & Announcements

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components