DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ
PA2521
N-CHANNEL MOS FET
FOR SWITCHING
DESCRIPTION
The
μ
PA2521 is N-channel MOS Field Effect Transistor
designed
for
DC/DC
converter
and
power
management
applications of portable equipments.
PACKAGE DRAWING (Unit: mm)
2.9±0.1
0.65
8
5
0 to 0.025
A
0.17±0.05
2.8±0.1
•
Low on-state resistance
R
DS(on)1
= 16.5 mΩ MAX. (V
GS
= 10 V, I
D
= 8.0 A)
R
DS(on)2
= 25 mΩ MAX. (V
GS
= 4.5 V, I
D
= 4.0 A)
•
Small and surface mount package (8-pin VSOF (2429))
•
Pb-free (This product does not contain Pb in external electrode
and other parts.)
•
Built-in gate protection diode
2.4±0.1
FEATURES
0.32±0.05
0.05 M S A
0.8±0.05
1, 2, 3 : Source
4
: Gate
5, 6, 7, 8: Drain
S
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
Note2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T1
P
T2
T
ch
T
stg
30
±20
±8
±32
1.0
2.2
150
−55
to +150
8
6.4
V
V
A
A
W
W
°C
°C
A
mJ
Gate
Protection
Diode
Source
Gate
EQUIVALENT CIRCUIT
Drain
Total Power Dissipation
Channel Temperature
Storage Temperature
Total Power Dissipation (PW = 5 sec)
Body
Diode
Single Avalanche Current
Single Avalanche Energy
Note3
Note3
I
AS
E
AS
Notes 1.
PW
≤
10
μ
s, Duty Cycle
≤
1%
2.
Mounted on FR-4 board of 25.4 mm x 25.4 mm x 0.8 mmt
3.
Starting T
ch
= 25°C, V
DD
= 15 V, R
G
= 25
Ω,
V
GS
= 20
→
0 V, L = 100
μ
H
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G19187EJ1V0DS00 (1st edition)
Date Published March 2008 NS
Printed in Japan
(0.3)
1
4
2008
μ
PA2521
ELECTRICAL CHARACTERISTICS (T
A
= 25°C, All terminals are connected.)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Cut-off Voltage
Forward Transfer Admittance
Note
Note
SYMBOL
I
DSS
I
GSS
V
GS(off)
| y
fs
|
R
DS(on)1
R
DS(on)2
TEST CONDITIONS
V
DS
= 30 V, V
GS
= 0 V
V
GS
=
±20
V, V
DS
= 0 V
V
DS
= 10 V, I
D
= 1 mA
V
DS
= 10 V, I
D
= 4.0 A
V
GS
= 10 V, I
D
= 8.0 A
V
GS
= 4.5 V, I
D
= 4.0 A
V
DS
= 15 V,
V
GS
= 0 V,
f = 1 MHz
V
DD
= 15 V, I
D
= 4.0 A,
V
GS
= 10 V,
R
G
= 10
Ω
MIN.
TYP.
MAX.
10
±10
UNIT
μ
A
μ
A
V
S
1.5
3.2
12
17
780
170
61
9.2
3.8
31
4.8
2.5
Drain to Source On-state Resistance
16.5
25
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Ω
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Gate Resistance
Note
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
R
G
V
DD
= 15 V,
V
GS
= 5 V,
I
D
= 8 A
I
F
= 8 A, V
GS
= 0 V
I
F
= 8 A, V
GS
= 0 V,
di/dt = 100 A/
μ
s
f = 1 MHz
7.6
2.6
2.4
0.82
24
17
1.6
Note
Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
R
G
= 25
Ω
PG.
V
GS
= 20
→
0 V
50
Ω
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
V
DD
PG.
R
G
R
L
V
DD
V
GS
V
GS
Wave Form
0
10%
V
GS
90%
V
DS
90%
90%
10%
10%
BV
DSS
I
AS
I
D
V
DD
V
DS
V
GS
0
τ
τ
= 1
μ
s
Duty Cycle
≤
1%
V
DS
V
DS
Wave Form
0
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= 2 mA
PG.
50
Ω
R
L
V
DD
2
Data Sheet G19187EJ1V0DS
μ
PA2521
TYPICAL CHARACTERISTICS (T
A
= 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
FORWARD BIAS SAFE OPERATING AREA
100
I
D(pulse)
PW
1
i
120
dT - Percentage of Rated Power - %
100
I
D
- Drain Current - A
10
I
D(DC)
1
i
0
=
1
i
0
Po
w
m
s
i
1
i
0
0
m
μ
s
i
80
60
40
20
0
0
20
40
60
80
100 120 140 160
T
A
- Ambient Temperature -
°C
0
s
1
d
it e
im V )
L
)
on
1
i
0
S(
=
D
R
GS
(V
er
D
5
i
s
is
si
m
s
i
pa
t io
n
Li
m
it e
d
0.1
Single Pulse
Mounted on FR-4 board of
25.4 mm x 25.4 mm x 0.8 mmt
0.01
0.01
0.1
1
10
100
V
DS
- Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
r
th(t)
- Transient Thermal Resistance -
°C/W
1000
R
th(ch-A)
= 125°C/Wi
100
10
1
Single Pulse
Mounted on FR-4 board of 25.4 mm x 25.4 mm x 0.8 mmt
0.1
100
μ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
30
10 V
4.5 V
4.0 V
3.8 V
3.6 V
I
D
- Drain Current - A
30
V
DS
= 10 V
Pulsed
20
I
D
- Drain Current - A
20
3.4 V
10
3.2 V
V
GS
= 3.0 V
Pulsed
0
0
0.2
0.4
0.6
0.8
1
V
DS
- Drain to Source Voltage - V
10
T
A
= 125°C
75°C
25°C
−25°C
0
0
1
2
3
4
V
GS
- Gate to Source Voltage - V
Data Sheet G19187EJ1V0DS
3
μ
PA2521
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
V
GS(off)
- Gate to Source Cut-off Voltage - V
| y
fs
| - Forward Transfer Admittance - S
3
10
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
2
1
T
A
= 125°C
75°C
25°C
−55°C
1
V
DS
= 10 V
I
D
= 1 mA
0
-75
-25
25
75
125
175
0.1
V
DS
= 10 V
Pulsed
0.01
0.01
0.1
1
10
100
T
ch
- Channel Temperature -
°C
I
D
- Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
R
DS(on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
R
DS(on)
- Drain to Source On-state Resistance - mΩ
40
Pulsed
30
40
30
20
V
GS
= 4.5 V
20
10
10 V
10
I
D
= 8.0 A
Pulsed
0
0
5
10
15
20
V
GS
- Gate to Source Voltage - V
0
0.1
1
10
100
I
D
- Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
R
DS(on)
- Drain to Source On-state Resistance - mΩ
40
Pulsed
30
V
GS
= 4.5 V, I
D
= 4.0 A
20
10 V, 8.0 A
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
10000
C
iss
, C
oss
, C
rss
- Capacitance - pF
1000
C
iss
100
V
GS
= 0 V
f = 1 MHz
10
0.1
1
10
C
oss
C
rss
10
0
-75
-25
25
75
125
175
100
T
ch
- Channel Temperature -
°C
V
DS
- Drain to Source Voltage - V
4
Data Sheet G19187EJ1V0DS
μ
PA2521
DYNAMIC INPUT CHARACTERISTICS
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
6
V
GS
- Gate to Source Voltage - V
I
F
- Diode Forward Current - A
100
10 V
V
DD
= 6 V
15 V
24 V
10
V
GS
= 4.5 V
1
0V
5
4
3
2
1
0.1
Pulsed
0.01
I
D
= 8 A
0
0
2
4
6
8
10
Q
G
- Gate Charge - nC
0
0.2
0.4
0.6
0.8
1
1.2
V
F(S-D)
- Source to Drain Voltage - V
ORDERING INFORMATION
PART NUMBER
LEAD PLATING
Note
Note
PACKING
8 mm embossed taping
3000 p/reel
PACKAGE
8-pin VSOF (2429)
μ
PA2521T1H-T1-AT
μ
PA2521T1H-T2-AT
Pure Sn
Note
Pb-free (This product does not contain Pb in external electrode and other parts.)
Data Sheet G19187EJ1V0DS
5
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