CY7C1348G-133AXC datasheet, PDF

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CY7C1348G-133AXC: Description4-Mbit (128K x 36) Pipelined DCD Sync SRAM; File Size345KB，16 Pages; ManufacturerCypress Semiconductor

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CY7C1348G-133AXC Overview

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

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CY7C1348G

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

• 128K × 36 common I/O architecture

• 3.3V core power supply (V

)

• 3.3V/2.5V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous Output Enable

• Available in lead-free 100-Pin TQFP package

• “ZZ” Sleep Mode option

Functional Description

[1]

The CY7C1348G SRAM integrates 128K x 36 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and CE

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW

[A:D]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the byte write control inputs. GW active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

The CY7C1348G operates from a +3.3V core power supply

while all outputs operate with a +3.3V or a +2.5V supply. All

inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

250 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

2.6

325

200 MHz

2.8

265

166 MHz

3.5

240

133 MHz

4.0

225

Unit

Note:

1. For best-practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05608 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised July 5, 2006

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