EEWORLDEEWORLDEEWORLD

Part Number

Search

LVA356AB

Description
Zener Diode, 5.6V V(Z), 5%, 0.4W, Silicon, Unidirectional, DO-7
CategoryDiscrete semiconductor    diode   
File Size29KB,1 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

LVA356AB Overview

Zener Diode, 5.6V V(Z), 5%, 0.4W, Silicon, Unidirectional, DO-7

LVA356AB Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCobham PLC
package instructionO-LALF-W2
Reach Compliance Codeunknown
ECCN codeEAR99
Is SamacsysN
Other featuresLOW NOISE, LOW LEVEL, LOW IMPEDANCE, LOW VOLTAGE AVALANCHE
Shell connectionISOLATED
ConfigurationSINGLE
Diode component materialsSILICON
Diode typeZENER DIODE
JEDEC-95 codeDO-7
JESD-30 codeO-LALF-W2
JESD-609 codee0
Number of components1
Number of terminals2
Package body materialGLASS
Package shapeROUND
Package formLONG FORM
Peak Reflow Temperature (Celsius)NOT SPECIFIED
polarityUNIDIRECTIONAL
Maximum power dissipation0.4 W
Certification statusNot Qualified
Nominal reference voltage5.6 V
surface mountNO
technologyZENER
Terminal surfaceTIN LEAD
Terminal formWIRE
Terminal locationAXIAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Maximum voltage tolerance5%
Working test current1 mA
Base Number Matches1
Please help me, why can't the HEX digital tube and OUTS simulation be done? A novice needs help.
module dj (clk_27m,rst_n,fangxiang,sudu,outf,outs,count_gd,HEX1,HEX2,HEX3,HEX4);input clk_27m;input rst_n;input fangxiang;input sudu;input count_gd;output outf,outs;output [6:0]HEX1,HEX2,HEX3,HEX4;reg...
关耳008 FPGA/CPLD
The problem of signal output affecting the circuit!
I encountered a strange problem. If I assign a signal in the circuit to an output pin, the logic of the entire circuit is wrong. (If it is not output, the logic is correct when observed through other ...
eeleader FPGA/CPLD
A low power consumption reference voltage circuit operating in subthreshold region
A low power consumption reference voltage circuit operating in subthreshold region...
linda_xia Analog electronics
Playing with Zynq Serial 44——[ex63] Image smoothing processing of MT9V034 camera
1 System Overview As shown in the figure, this is the principle block diagram of the entire video acquisition system. At the beginning of power-on, the FPGA needs to initialize the register configurat...
ove学习使我快乐 FPGA/CPLD
Need code urgently
Can anyone tell me the code to collect carbon monoxide concentration?...
懵懂的小孩子 51mcu
[2022 Digi-Key Innovation Design Competition] Material Unboxing STM32H745I-DISCO
First of all, I would like to thank Digi-KeyEEWORLD for providing the opportunity. I placed an order with Digi-Key on the evening of June 15th, and received a notification from SF-Express on the 27th ...
Juggernaut DigiKey Technology Zone

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1279  514  1336  282  2613  26  11  27  6  53 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号