Revision 2
Extended Temperature Fusion Family of Mixed Signal FPGAs
Features and Benefits
Extended Temperature Tested
•
•
•
•
•
•
Each Device Tested from –55°C to 100°C Junction Temperature
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program when Powered Off
Instant On Single-Chip Solution
350 MHz System Performance
User Flash Memory – 4 Mbits to 8 Mbits
– Configurable 16- or 32-Bit Datapath
– 10 ns Access in Read-Ahead Mode
1 Kbit of Additional FlashROM
Up to 12-Bit Resolution and Up to 600 Ksps
Internal 2.56 V or External Reference Voltage
ADC: 30 Scalable Analog Input Channels
High-Voltage Input Tolerance: –10.5 V to +12 V
Current Monitor
†
and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
– P- and N-Channel Power MOSFET Support
– Programmable 1, 3, 10, 30 µA, and 20 mA Drive Strengths
ADC Accuracy Is Better than 1%
•
6 Clock Conditioning Circuits (CCCs) with 2 Integrated PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
Sleep and Standby Low-Power Modes
ISP with 128-Bit AES via JTAG
FlashLock
®
Designed to Secure FPGA Contents
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS
– Built-In I/O Registers
– 700 Mbps DDR Operation
Hot-Swappable I/Os
Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Pull-Down Resistor
Pin-Compatible Packages across the Fusion
®
Family
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9, and
×18 organizations available)
True Dual-Port SRAM (except ×18)
Programmable Embedded FIFO Control Logic
ARM Cortex-M1–Enabled
High-Performance Reprogrammable Flash Technology
Low Power Consumption
•
•
•
•
•
•
•
In-System Programming (ISP) and Security
Advanced Digital I/O
Embedded Flash Memory
•
•
•
•
•
•
•
Integrated A/D Converter (ADC) and Analog I/O
•
•
•
•
•
•
•
•
•
SRAMs and FIFOs
On-Chip Clocking Support
• I
nternal 100 MHz RC Oscillator (Accurate to 1%)
•
•
Crystal Oscillator Support (32 KHz to 20 MHz)
Programmable Real-Time Counter (RTC)
Soft ARM
®
Cortex™- M1 Fusion Devices (M1)
Table 1 • Fusion Extended Temperature Devices
Fusion Devices
ARM
Cortex-M1
*
Devices
System Gates
Tiles (D-flip-flops)
General Information
Secure (AES) ISP
PLLs
Globals
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
Memory
FlashROM Bits
RAM Blocks (4,608 bits)
RAM kbits
Analog Quads
Analog Input Channels
Analog and I/Os
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
Analog I/Os
AFS600
M1AFS600
600,000
13,824
Yes
2
18
2
4M
1,024
24
108
10
30
10
5
172
40
AFS1500
M1AFS1500
1,500,000
38,400
Yes
2
18
4
8M
1,024
60
270
10
30
10
5
223
40
Note:
*Refer to the
Cortex-M1
product brief for more information.
† Refer to
Table 2 on page IV
for details.
January 2013
© 2013 Microsemi Corporation
I
Extended Temperature Fusion Family of Mixed Signal FPGAs
Fusion Device Architecture Overview
Bank 0
Bank 1
CCC
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
OSC
I/Os
CCC/PLL
VersaTile
Bank 4
Bank 2
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Flash Memory Blocks
ADC
Flash Memory Blocks
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
CCC
Figure 1 •
Bank 3
Fusion Device Architecture Overview (AFS600)
Package I/Os: Single-/Double-Ended (Analog)
Fusion Devices
ARM Cortex-M1 Devices
FG256
FG484
AFS600
M1AFS600
119/58 (40)
172/86 (40)
AFS1500
M1AFS1500
119/58 (40)
223/109 (40)
II
R ev i si o n 2
Extended Temperature Fusion Family of Mixed Signal FPGAs
Product Ordering Codes
M1AFS600
_
1
FG
G
256
Y
K
Application (junction temperature range)
K = Extended Temperature (–55°C to 100°C)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging Options
Blank = Standard Packaging
G = RoHS-Compliant (green) Packaging
Package Type
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
Fusion Devices
AFS600 = 600,000 System Gates
AFS1500 = 1,500,000 System Gates
ARM-Enabled Fusion Devices
M1AFS600 = 600,000 System Gates
M1AFS1500 = 1,500,000 System Gates
Fusion Device Status
Fusion
AFS600
AFS1500
Status
Production
Production
Cortex-M1
M1AFS600
M1AFS1500
Status
Production
Production
Temperature Grade Offerings
Fusion Devices
ARM Cortex-M1 Devices
FG256
FG484
AFS600
M1AFS600
C, I, K
C, I, K
AFS1500
M1AFS1500
C, I, K
C, I, K
Notes:
1. C = Commercial Temperature Range: 0°C to 85°C Junction. Refer to the commercial
Fusion datasheet
for details.
2. I = Industrial Temperature Range: –40°C to 100°C Junction. Refer to the commercial
Fusion datasheet
for details.
3. K = Extended Temperature Range: –55°C to 100°C Junction
R e visi on 2
III
Extended Temperature Fusion Family of Mixed Signal FPGAs
Speed Grade and Temperature Grade Matrix
Std
K
–1
–2
AFS600
AFS1500
M1AFS600
M1AFS1500
AFS600
AFS1500
M1AFS600
M1AFS1500
NA
Note:
K = Extended Temperature Range: –55°C to 100°C Junction
Summary of Differences Between Extended Temperature and
Commercial/Industrial Grade Devices
Table 2 • Summary of Differences
Feature*
Temperature (junction)
AV (negative voltage input)
AC (positive voltage input)
Sleep mode
Pigeon Point ATCA IP support (P1)
MicroBlade Advanced Mezzanine Card support
(U1)
Remainder of features
Extended Temperature
–55°C to 100°C
Not supported between –40°C to –55°C
Not supported between –40°C to –55°C
Not supported between –40°C to –55°C
Not Supported
Not Supported
Supported across all temperatures
Commercial/Industrial
Temperature
0°C to 85°C / –40°C to 100°C
Supported across all temperatures
Supported across all temperatures
Supported across all temperatures
Supported across all temperatures
Supported across all temperatures
Supported across all temperatures
Note:
*This table lists only the differences in features. For additional details, refer to the
"Device Architecture" section on page 2-1
and the
"DC and Power Characteristics" section on page 3-1.
Software Considerations for Extended Temperature Fusion
Selection Wizard. This enables the option of selecting the
EXT
temperature range under operating conditions.
When designing with Libero
®
System-on-Chip (SoC) software,
select the K package (example: 256 FBGA K) in the Device
Device Availability
Contact your local Microsemi SoC Products Group representative for device availability:
(http://www.microsemi.com/soc/contact/offices/index.html).
IV
R ev i si o n 2
Extended Temperature Fusion Family of Mixed Signal FPGAs
Table of Contents
Fusion Device Family Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Unprecedented Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Device Architecture
Fusion Stack Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Real-Time Counter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Analog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76
Analog Configuration MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-126
User I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-222
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-227
DC and Power Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Pin Assignments
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Revision 2
V
Renesas Electronics MCUs
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