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SN74ALVCH16721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES052E – JULY 1995 – REVISED AUGUST 2004
FEATURES
•
•
•
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
•
•
DESCRIPTION
This 20-bit flip-flop is designed specifically for 1.65-V
to 3.6-V V
CC
operation.
The 20 flip-flops of the SN74ALVCH16721 are
edge-triggered D-type flip-flops with qualified clock
storage. On the positive transition of the clock (CLK)
input, the device provides true data at the Q outputs if
the clock-enable (CLKEN) input is low. If CLKEN is
high, no data is stored.
A buffered output-enable (OE) input places the 20
outputs in either a normal logic state (high or low) or
the high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without
need for interface or pullup components. OE does not
affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the
outputs are in the high-impedance state.
OE
Q1
Q2
GND
Q3
Q4
V
CC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
V
CC
Q17
Q18
GND
Q19
Q20
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLK
D1
D2
GND
D3
D4
V
CC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
V
CC
D17
D18
GND
D19
D20
CLKEN
NC − No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16721 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated
www.ti.com
SN74ALVCH16721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES052E – JULY 1995 – REVISED AUGUST 2004
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage
range
(2)
V
I
< 0
V
O
< 0
Output voltage range
(2) (3)
Input clamp current
Output clamp current
Continuous output current
Continuous current through each V
CC
or GND
DGG package
θ
JA
T
stg
(1)
(2)
(3)
(4)
Package thermal
impedance
(4)
DGV package
DL package
Storage temperature range
-65
-0.5
-0.5
-0.5
MAX
4.6
4.6
V
CC
+ 0.5
-50
-50
±50
±100
81
86
74
150
°C
°C/W
UNIT
V
V
V
mA
mA
mA
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
V
CC
V
IH
Supply voltage
V
CC
= 1.65 V to 1.95 V
High-level input voltage
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 1.65 V to 1.95 V
V
IL
V
I
V
O
Low-level input voltage
Input voltage
Output voltage
V
CC
= 1.65 V
I
OH
High-level output current
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3 V
V
CC
= 1.65 V
I
OL
Low-level output current
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3 V
∆t/∆v
T
A
(1)
Input transition rise or fall rate
Operating free-air temperature
-40
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
0
0
1.65
0.65
×
V
CC
1.7
2
0.35
×
V
CC
0.7
0.8
V
CC
V
CC
-4
-12
-12
-24
4
12
12
24
10
85
ns/V
°C
mA
mA
V
V
V
V
MAX
3.6
UNIT
V
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
3
SN74ALVCH16721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES052E – JULY 1995 – REVISED AUGUST 2004
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
I
OH
= -100 µA
I
OH
= -4 mA
I
OH
= -6 mA
V
OH
I
OH
= -12 mA
I
OH
= -24 mA
I
OL
= 100 µA
I
OL
= 4 mA
V
OL
I
OL
= 6 mA
I
OL
= 12 mA
I
OL
= 24 mA
I
I
V
I
= V
CC
or GND
V
I
= 0.58 V
V
I
= 1.07 V
V
I
= 0.7 V
I
I(hold)
V
I
= 1.7 V
V
I
= 0.8 V
V
I
= 2 V
V
I
= 0 to 3.6
I
OZ
I
CC
∆I
CC
C
i
C
o
(1)
(2)
Control inputs
Data inputs
Outputs
V
(2)
I
O
= 0
Other inputs at V
CC
or GND
V
O
= V
CC
or GND
V
I
= V
CC
or GND,
One input at V
CC
- 0.6 V,
V
I
= V
CC
or GND
V
O
= V
CC
or GND
TEST CONDITIONS
V
CC
1.65 V
2.3 V
2.3 V
2.7 V
3V
3V
1.65 V to 3.6 V
1.65 V
2.3 V
2.3 V
2.7 V
3V
3.6 V
1.65 V
1.65 V
2.3 V
2.3 V
3V
3V
3.6 V
3.6 V
3.6 V
3 V to 3.6 V
3.3 V
3.3 V
3.5
6
7
25
-25
45
-45
75
-75
±500
±10
40
750
µA
µA
µA
pF
pF
µA
MIN
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
±5
µA
V
V
TYP
(1)
MAX
UNIT
1.65 V to 3.6 V V
CC
- 0.2
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
V
CC
= 1.8 V
MIN
f
clock
t
w
t
su
th
(1)
Clock frequency
Pulse duration, CLK high or low
Setup time
Hold time
Data before CLK↑
CLKEN before CLK↑
Data after CLK↑
CLKEN after CLK↑
(1)
(1)
(1)
(1)
(1)
V
CC
= 2.5 V
±
0.2 V
MIN
3.3
4
3.4
0
0
MAX
150
V
CC
= 2.7 V
MIN
3.3
3.6
3.1
0
0
MAX
150
V
CC
= 3.3 V
±
0.3 V
MIN
3.3
3.1
2.7
0
0
MAX
150
UNIT
MHz
ns
ns
ns
MAX
(1)
This information was not available at the time of publication.
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