EDI88512C
HI-RELIABILITY PRODUCT
512Kx8 Monolithic SRAM CMOS
FEATURES
s
512Kx8 bit CMOS Static
s
Random Access Memory
• Access Times of 70, 85, 100ns
• Data Retention Function (LP version)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
s
32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic SOJ (Package 140)
s
Single +5V (±10%) Supply Operation
The EDI88512C is a 4 megabit Monolithic CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard
for the four megabit device. Both the DIP and CSOJ packages are
pin for pin upgrades for the single chip enable 128K x 8, the
EDI88128C. Pins 1 and 30 become the higher order addresses.
A Low Power version with Data Retention (EDI88512LP) is also
available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION
PIN DESCRIPTION
TOP VIEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 V
CC
31 A15
30 A17
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
I/O
0-7
A
0-18
WE
CS
OE
V
CC
V
SS
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V
±10%)
Ground
Not Connected
BLOCK DIAGRAM
Memory Array
A
Ø-18
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
Ø-7
WE
CS
OE
February 2001 Rev. 11
1
White Electronic Designs Corporation • www.whiteedc.com • (602) 437-1520
EDI88512C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature T
A
(Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, T
J
0 to +70
-40 to +85
-55 to +125
-65 to +150
1
20
175
°C
°C
°C
°C
W
mA
°C
-0.5 to 7.0
Unit
V
OE
X
H
L
X
CS
H
L
L
L
WE
X
H
H
L
TRUTH TABLE
Mode
Standby
Output Deselect
Read
Write
Output
High Z
High Z
Data Out
Data In
Power
Icc
2
, Icc3
Icc
1
Icc
1
Icc
1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
Vcc +0.5
+0.8
Unit
V
V
V
V
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C)
Parameter
Address Lines
Data Lines
Symbol
C
I
C
O
Condition
V
IN
= Vcc or Vss, f = 1.0MHz
V
OUT
= Vcc or Vss, f = 1.0MHz
Max Unit
12
14
pF
pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
(V
CC
= 5V, *T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
WE, CS = V
IL
, I
I/O
= 0mA, Min Cycle (70-100ns)
CS
≥
V
IH
, V
IN
≤
V
IL
, V
IN
≥
V
IH
CS
≥
V
CC
-0.2V
V
IN
≥
Vcc -0.2V or V
IN
≤
0.2V
I
OL
= 2.1mA
I
OH
= -1.0mA
C
LP
Conditions
Min
—
—
—
—
—
—
—
2.4
Typ*
—
—
45
3
—
—
—
—
Max
±10
±10
75
10
5
2
0.4
—
Units
µA
µA
mA
mA
mA
mA
V
V
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480Ω
480Ω
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
V
SS
to 3.0V
5ns
1.5V
Figure 1
Q
255Ω
30pF
Q
255Ω
5pF
NOTE:
For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
2
EDI88512C
AC CHARACTERISTICS – READ CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0°C to +70°C)
Symbol
JEDEC
Alt.
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
EHQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
t
RC
t
AA
t
ACS
t
CLZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
5
0
25
10
35
5
0
30
10
25
10
45
5
0
30
70ns
Min
70
70
70
10
30
10
50
Max
Min
85
85
85
10
30
85ns
Max
Min
100
100
100
100ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0°C to +70°C)
Symbol
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
JEDEC
t
AVAV
t
ELWH
t
ELEH
t
AVWL
t
AVEL
t
AVWH
t
AVEH
t
WLWH
t
WLEH
t
WHAX
t
EHAX
t
WHDX
t
EHDX
t
WLQZ
t
DVWH
t
DVEH
t
WHQX
Alt.
t
WC
t
CW
t
CW
t
AS
t
AS
t
AW
t
AW
t
WP
t
WP
t
WR
t
WR
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
WLZ
Min
70
60
60
0
0
65
65
50
50
0
0
0
0
0
40
30
5
25
70ns
Max
Min
85
70
70
0
0
70
70
55
55
0
0
0
0
0
40
35
5
30
85ns
Max
Min
100
80
80
0
0
80
80
60
60
0
0
0
0
0
40
40
5
30
100ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
3
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
EDI88512C
FIG. 2
TIMING WAVEFORM - READ CYCLE
ADDRESS
t
AVAV
t
AVQV
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
CS
t
ELQV
t
ELQX
OE
t
EHQZ
t
AVQV
DATA I/O
t
AVQX
DATA 1
DATA 2
t
GLQV
t
GLQX
DATA OUT
t
GHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3
WRITE CYCLE - WE CONTROLLED
t
AVAV
ADDRESS
t
AVWH
t
ELWH
CS
t
WHAX
t
AVWL
WE
t
WLWH
t
DVWH
t
WHDX
DATA IN
DATA VALID
t
WLQZ
DATA OUT
HIGH Z
t
WHQX
WRITE CYCLE 1, WE CONTROLLED
FIG. 4
WRITE CYCLE - CS CONTROLLED
ADDRESS
t
AVAV
WS32K32-XHX
t
AVEH
t
ELEH
t
EHAX
t
AVEL
t
WLEH
t
DVEH
t
EHDX
CS
WE
DATA IN
DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
4
EDI88512C
DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY)
(T
A
= -55°C to +125°C)
Characteristic
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time
Operation Recovery Time
Sym
V
DD
I
CCDR
T
CDR
T
R
Conditions
V
DD
= 2.0V
CS
≥
V
DD
-0.2V
V
IN
≥
V
DD
-0.2V
or V
IN
≤
0.2V
Min
2
–
0
T
AVAV
Typ
–
–
–
–
Max
–
185
–
–
Units
V
µA
ns
ns
FIG. 5
DATA RETENTION - CS CONTROLLED
Data Retention Mode
Vcc
4.5V
V
DD
WS32K32-XHX
4.5V
t
CDR
CS
CS = V
DD
-0.2V
t
R
DATA RETENTION, CS CONTROLLED
5
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
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