Synchronous Rectifier Driver with Power Up/Down Control,
Output OVP, Error Amplifier and Precision Reference
DESCRIPTION
The SiP11203/SiP11204 provide the secondary side
error amplifier, reference voltage and synchronous
rectifier drivers for isolated converter topologies. Both
ICs are capable of being powered via conventional
bias supplies (output inductor winding or power trans-
former winding), or from a pulse transformer supplying
the gate timing signals, and both parts generate a reg-
ulated supply for powering the error amplifier and con-
trol circuitry.
During power-up the SiP11203/SiP11204 ensure that
the synchronous rectifiers are held off until the supply
voltages are adequate to guarantee effective opera-
tion of the driver circuits. During the soft-start interval,
a gradual ramp-up of the synchronous rectifier con-
duction time is provided. Both ICs also allow control of
the discharge rate of the synchronous rectifier driver
outputs during power-down.
The SiP11203 and SiP11204 are available in a
Pb-free MLP44-16 package and are rated to handle
the industrial ambient temperature range of - 40 to 85 °C.
FEATURES
• High Current synchronous rectifier drivers
- 2.2 A source and 4 A sink
• Driver switching synchronized with primary
controller
• Full output control during power-up and power-
down
• 5.5 V to 13 V operating voltage range
• 1.225 V on board bandgap voltage reference
• Can be powered from the pulse transformer supply-
ing synchronous rectifier timing signals
• On-chip ground-sensing error amplifier
• Programmable rising edge delay
• Output over-voltage protection (OVP)
- SiP11203 turns synchronous rectifiers on
- SiP11204 turns synchronous rectifiers off
• Secondary-side companion chip for the Si9122
Half-Bridge Controller IC
APPLICATIONS
• High efficiency DC-DC Converter Modules and
Bricks
• Telecom and Server Power Supplies
• High Efficiency Intermediate Bus Converters (IBC)
• Half-bridge, full-bridge, or push-pull primary DC-DC
topologies
• Center-tapped or current-doubler secondary con-
figurations
TYPICAL APPLICATION CIRCUIT
V
IN
Half Bridge
PWM
Controller
V
OUT
OUT A
OVPin
EA+
SiP11203
SiP11204
EA-
Vref
EAout
PGND
GND
GND
SRH
SRL
Pulse
Transformer
OUT B
Vin
IN A
IN B
GND
VL
Cpd
Rdel
Rpd
Optoisolator
ZF2
ZF1
Document Number: 73868
S-Pending–Rev. A, 02-May-06
www.vishay.com
1
Work-in-Progress
SiP11203/SiP11204
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
V
IN
, IN
A
, IN
B
V
REF
, Linear Inputs
Storage Temperature
Junction Temperature
Package Thermal Impedance (Rθ
JA
)
16 Pin 44MLP
Package Power Dissipation (package)
a
Limit
15
- 0.3 V to V
L
+ 0.3 V
- 65 to + 160
- 40 to +125
47
745
°C
°C/W
mW
Unit
V
Notes:
a. Device mounted with all leads soldered to printed circuit board.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Parameter
V
IN
C
VIN
C
VL
C
REF
Linear Inputs (EA+, EA-, OVP
IN
)
Error Amplifier Output Voltage
Logic Inputs (IN
A
, IN
B
)
Reference voltage output current
R
PD
C
PD
Limit
5.5 to 13
1
1
0.1
0 to V
L
0 to 3.5
0 to 13
10
> 15
1 to 10
Unit
V
µF
V
µA
kΩ
nF
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
5.5 V
≤
V
IN
≤
13 V
T
A
= - 40 to 85 °C
Output disabled (Note e)
(Note c)
I
L
= 0 mA
I
L
= 0 mA to 3.3 mA, V
IN
= 5.5 V
f
TEST
=100 Hz, (Note c)
V
IN
= 5.5 V, C
LOAD(A)
= C
LOAD(B)
= 6 nF (Note c, d)
V
IN
= 7.5 V, C
LOAD(A)
= C
LOAD(B)
= 6 nF (Note c, d)
Device switching disabled (Note e)
Current sourced from V
IN
to V
L
, V
L
= 0 V
I
REF2
= 0 mA, T
A
= 25 °C
I
REF2
= 0 mA
(Note c)
V
IN
= 5.5 V, I
REF
= 0 to 10 µA
f
TEST
= 100 Hz, (Note c)
V
IN
= 5.5 V, measured at R
PD
pin
2.320
35
1.212
1.188
Limits
Parameter
Power Supply
V
L
Output Voltage
V
L
Temperature Coefficient
V
L
Line Regulation
V
L
Load Regulation
V
L
Supply PSRR
Supply Current
Quiescent Current
Start-up Current Capability
Reference Voltages
V
REF
Voltage
V
REF
Temperature Coefficient
V
REF
Load Regulation
V
REF
PSRR
Internal Buffered Reference Voltage
www.vishay.com
2
Symbol
V
L
TC1
V
L_LNR
V
L_LDR
V
L_PSRR
I
IN
I
Q
I
STARTUP
Min
a
4.75
Typ
b
5.0
160
3
1.2
70
12
15.5
3.5
45
1.225
1.225
160
1.5
60
2.5
Max
a
5.25
8
10
Unit
V
µV/°C
mV
dB
4.5
55
1.238
1.262
2.5
2.570
mA
V
REF
TC2
V
REF_LDR
V
REF_PSRR
V
REFINT
V
µV/°C
mV
dB
V
Document Number: 73868
S-Pending–Rev. A, 02-May-06
SiP11203/SiP11204
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
5.5 V
≤
V
IN
≤
13 V
T
A
= - 40 to 85 °C
Rising
Falling
V
IN
= 13 V, 13 V at INA and/or INB
(Note c)
20 log (ΔV
OUT
/ΔV
OS
) for V
OUT
= 0.5 V to 3.0 V
Input CMR = 0 V to 3.5 V
V
CM
= 1.225 V, R
LOAD
= 10 kΩ to V
CM
(Note c)
V
CM
= 1.225 V
(I
EA+
) - (I
EA-
), (Note c)
Output sinking 0.8 mA
Output sourcing 0.8 mA
Sourcing, EA
OUT
= 1.0 V, EA+ overdrive = 500 mV
Sinking, EA
OUT
= 2.5 V, EA+ overdrive = 500 mV
(Note c)
Rising, R
LOAD
= 2 kΩ II 1 nf to Ground
Falling, R
LOAD
= 2 kΩ II 1 nf to Ground
3.0
3.5
0.8
3.0
100
65
60
70
65
±3
30
2
± 0.3
225
3.45
4.7
1.3
1
0.75
1
2.3
1.5
2.1
1.4
1.2
2.4
2.2
4.0
45
42
35
32
20
20
32
34
55
55
0
28
38
25
48
µs
ns
A
3.7
2.4
3.4
2.2
Ω
400
10
± 15
Limits
Parameter
Logic Inputs - IN A and IN B
Input High
Input Low
Input Resistance
Input Frequency Range (INA and INB)
Symbol
V
IH
V
IL
R
IN
f
IN
Min
a
4.0
Typ
b
2.5
2.1
3.8
Max
a
Unit
1.0
4.5
500
V
kΩ
kHz
Error Amplifier - DC Electrical Characteristics
A
V
Voltage Gain
Common Mode Rejection Ratio
Input Offset Voltage
V
OS
Temperature Coefficient
Input Bias Current
Input Offset Current
Output Voltage
Output Current
CMRR
V
OS
TC3
I
BIAS
I
OS
V
OL
V
OH
I
OH
I
OL
dB
mV
µV/°C
nA
mV
V
mA
Error Amplifier - AC Electrical Characteristics
BW
Gain-Bandwidth Product
Slew Rate
MOSFET Drivers
R
D(SOURCE)
Driver Impedance
R
D(SINK)
R
D(SOURCE)
R
D(SINK)
I
PK(SOURCE)
Peak Drive Current
I
PK(SINK)
I
PK(SOURCE)
I
PK(SINK)
Rise Time
Fall Time
t
r
t
f
t
pdr
IN to OUT Propagation Delay
t
pdf
Additional Rising Edge OUT A/B
Delay vs. R
DEL
Power-down Detection Timeout
Δt
DELAY
t
PDDET
SR+
SR-
MHz
V/µs
V
IN
= 5.5 V, I
OUT
= 100 mA, T
J
= 25 °C
V
IN
= 7.5 V, I
OUT
= 100 mA, T
J
= 25 °C
V
IN
= 5.5 V, T
J
= 25 °C (Note c)
V
IN
= 7.5 V, T
J
= 25 °C (Note c)
10 % to 90 %, V
IN
= 5.5 V, C
LOAD
= 6 nF, (Note c)
10 % to 90 %, V
IN
= 7.5 V, C
LOAD
= 6 nF, (Note c)
90 % to 10 %, V
IN
= 5.5 V, C
LOAD
= 6 nF, (Note c)
90 % to 10 %, V
IN
= 7.5 V, C
LOAD
= 6 nF, (Note c)
INA/INB rising to OUTA/OUTB rising, 50 % to 50 %
V
IN
= 5.5 V, R
DEL
connected to V
L
, C
LOAD
= 0 nF
INA/INB falling to OUTA/OUTB falling, 50 % to 50 %
V
IN
= 5.5 V, R
DEL
connected to V
L
, C
LOAD
= 0 nF
R
DEL
connected to V
L
R
DEL
= 25 kΩ to GND, C
LOAD
= 0 nF (Note d)
IN A and IN B low to OUT A/OUT B low
R
PD
= 25 kΩ, C
PD
= 1 nF (Note c)
No forcing voltage on V
IN
or V
L
, both V
IN
and V
L
bypassed by 1 µF to GND, INA or INB = 5 V, other
input = 0 V, force 1 V at active output (A or B)
Power-up Output Hold-off Current
I
HOFF
350
530
mA
Document Number: 73868
S-Pending–Rev. A, 02-May-06
www.vishay.com
3
SiP11203/SiP11204
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
5.5 V
≤
V
IN
≤
13 V
T
A
= - 40 to 85 °C
V
IN
Rising until output transitions on
V
IN
Falling until output transitions off
UVLO
R
- UVLO
F
, I
L
= 0 mA
Rising voltage on OVP
IN
to force OUTA and OUTB
high
Falling voltage on OVP
IN
to allow OUTA and OUTB
to go low
OVP
R
- OVP
F
V
IN
Rising until current at V
IN
> 1 mA
V
IN
Falling until current at V
IN
< 0.25 mA
CUVLO
R
- CUVLO
F
Limits
Parameter
Under Voltage Lockout Section
UVLO Threshold (Rising)
UVLO Threshold (Falling)
UVLO Hysteresis
Output Overvoltage Protection
Force Outputs On Threshold
Resume Normal Operation Threshold
Hysteresis
Housekeeping Supply Section
IC logic enable
IC logic disable
Hysteresis
Symbol
UVLO
R
UVLO
F
V
HYS(UVLO)
Min
a
4.3
2.9
1.25
Typ
b
4.45
3.05
1.40
Max
a
4.6
3.2
1.55
Unit
V
OVP
R
OVP
F
V
HYS(OVP)
CUVLO
R
CUVLO
F
V
HYS(CUVLO)
1.40
1.06
0.30
3.35
2.90
0.35
1.47
1.13
0.35
3.55
3.05
0.50
1.55
1.20
0.40
3.70
3.20
0.65
V
V
Notes:
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum and over - 40 °C to 85 °C.
b. Typical values are specified for 25 °C operation, and are for design reference only.
c. Not 100 % tested in production. This information is provided for reference only.
d. IN A or IN B switching at 250 kHz, R
DEL
= 25 kΩ to ground.
e. IN A = step 5 to 0 V and IN B = 5 V or vice versa, R
DEL
= 25 kΩ to ground, error amplifier configured as voltage follower with EA+ connected
to V
REF.
PIN CONFIGURATION
OUTB R
PD
C
PD
V
REF
16
15
14
13
12
11
10
9
5
6
7
8
V
REF
C
PD
R
PD
OUTB
13
14
15
16
1
2
3
4
8
7
6
5
INB
V
IN
PGND
INA
1
2
3
4
OVP
IN
EA+
EA-
EA
OUT
OVP
IN
EA+
EA-
EA
OUT
12
11
10
9
INB
V
IN
PGND
INA
OUTA GND R
DEL
V
L
V
L
R
DEL
GNDOUTA
Top
View
MLP44-16
Bottom
View
ORDERING INFORMATION
Part Number
Si11203DLP-T1-E3
Si11204DLP-T1-E3
Marking
11203
11204
Ambient Temperature Range
- 40 to 85 °C
www.vishay.com
4
Document Number: 73868
S-Pending–Rev. A, 02-May-06
SiP11203/SiP11204
Vishay Siliconix
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
INB
V
IN
PGND
INA
OUTA
GND
R
DEL
V
L
EA
OUT
EA-
EA+
OVP
IN
V
REF
C
PD
R
PD
OUTB
Function
Logic input for output driver B
Input supply voltage
Power ground
Logic input for output driver A
Driver output A
Analog ground (connect GND to the exposed pad of the IC package)
Sets output rising edge delay
5 V supply voltage for internal circuitry
Error amplifier output
Error amplifier inverting input
Error amplifier non inverting input
Input pin for over voltage detection
1.225 V reference voltage for converter output voltage regulating setting
Capacitor value sets power down detection time in conjunction with R
PD
Resistor value sets currents for power down detection timer and for power down discharge of outputs
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