Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
April 2013
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M
High-Speed 10 MBit/s Logic Gate Optocouplers
Features
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Description
The 6N137M, HCPL2601M, HCPL2611M single-channel
and HCPL2630M, HCPL2631M dual-channel optocou-
plers consist of a 850 nm AlGaAS LED, optically coupled
to a very high speed integrated photo-detector logic gate
with a strobable output. This output features an open col-
lector, thereby permitting wired OR outputs. The
switching parameters are guaranteed over the tempera-
ture range of -40°C to +85°C. A maximum input signal of
5 mA will provide a minimum output sink current of
13 mA (fan out of 8).
An internal noise shield provides superior common
mode rejection of typically 10 kV/µs. The HCPL2601M
and HCPL2631M has a minimum CMR of 5 kV/µs. The
HCPL2611M has a minimum CMR of 10 kV/µs.
Very High Speed – 10 MBit/s
Superior CMR – 10 kV/µs
Fan-out of 8 Over -40°C to +85°C
Logic Gate Output
Strobable Output
Wired OR-open Collector
U.L. Recognized (File # E90700, Vol. 2)
Applications
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Ground Loop Elimination
LSTTL to TTL, LSTTL or 5 V CMOS
Line Receiver, Data Transmission
Data Multiplexing
Switching Power Supplies
Pulse Transformer Replacement
Computer-peripheral Interface
Schematics
Package Outlines
N/C 1
8 V
CC
8
+ 1
V
F1
8 V
CC
1
8
1
+ 2
V
F
_
3
7 V
E
_ 2
7 V
01
8
6 V
O
_
V
3
6 V
02
8
1
1
F2
Figure 2. Package Options
5 GND
N/C 4
5 GND
+ 4
Truth Table
(Positive Logic)
Input
Enable
H
H
L
L
NC
NC
Output
L
H
H
H
L
H
www.fairchildsemi.com
6N137M
HCPL2601M
HCPL2611M
H
HCPL2630M
HCPL2631M
(Preliminary)
L
H
L
H
L
A 0.1µF bypass capacitor must be connected between pins 8 and 5
(1)
.
Figure 1. Schematics
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Safety and Insulation Ratings for 8-Pin DIP White
As per DIN_EN/IEC 60747-5-2. This optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.
Symbol
Parameter
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150 V
RMS
For Rated Mains Voltage < 300 V
RMS
For Rated Mains Voltage < 450 V
RMS
For Rated Mains Voltage < 600 V
RMS
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Min.
Typ.
I–IV
I–IV
I–III
I–III
40/100/21
2
Max.
Unit
CTI
V
PR
Comparative Tracking Index
Input to Output Test Voltage, Method b,
V
IORM
x 1.875 = V
PR
, 100% Production Test with
tm = 1 s, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a,
V
IORM
x 1.5 = V
PR
, Type and Sample Test with
tm = 60 s, Partial Discharge < 5 pC
175
1,669
1,335
V
IORM
V
IOTM
Max Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
External Clearance
External Clearance (for Option T, 0.4” Lead Spacing)
Insulation Thickness
Safety Limit Values, Maximum Values Allowed in the
Event of a Failure
890
6,000
8.0
7.4
10.16
0.5
V
PEAK
V
PEAK
mm
mm
mm
mm
T
S
I
S,INPUT
P
S,OUTPUT
R
IO
Case Temperature
Input Current
Output Power (Duty Factor
≤
2.7%)
Insulation Resistance at T
S
, V
IO
= 500 V
150
200
300
10
9
°C
mA
mW
Ω
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
www.fairchildsemi.com
2
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T
A
= 25°C unless otherwise specified.
Symbol
T
STG
T
OPR
T
SOL
Emitter
I
F
V
E
V
R
P
I
Detector
Supply Voltage
V
CC
(1 minute max)
I
O
V
O
P
O
Output Current
Output Voltage
Collector Output
Power Dissipation
DC/Average Forward
Input Current
Storage Temperature
Operating Temperature
Lead Solder Temperature
Parameter
Value
-40 to +125
-40 to +100
260 for 10 s
Units
°C
°C
°C
mA
V
V
mW
Single Channel
Dual Channel (Each Channel)
Single Channel
Each Channel
Single Channel
Dual Channel (Each Channel)
50
30
5.5
5.0
100
45
7.0
Enable Input Voltage Not to Exceed
V
CC
by more than 500 mV
Reverse Input Voltage
Power Dissipation
V
mA
V
mW
Single Channel
Dual Channel (Each Channel)
Each Channel
Single Channel
Dual Channel (Each Channel)
50
50
7.0
85
60
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
I
FL
I
FH
V
CC
V
EL
V
EH
T
A
N
Parameter
Input Current, Low Level
Input Current, High Level
Supply Voltage, Output
Enable Voltage, Low Level
Enable Voltage, High Level
Ambient Operating Temperature
Fan Out (TTL load)
Min.
0
*6.3
4.5
0
2.0
-40
Max.
250
15
5.5
0.8
V
CC
+85
8
Units
µA
mA
V
V
V
°C
*6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value
is 5.0 mA or less.
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
www.fairchildsemi.com
3
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Electrical Characteristics
(T
A
= 0 to 70°C unless otherwise specified)
Individual Component Characteristics
Symbol
EMITTER
V
F
B
VR
C
IN
Δ
V
F
/
Δ
T
A
DETECTOR
I
CCH
I
CCL
High Level Supply Current
Low Level Supply Current
V
CC
= 5.5 V, I
F
= 0 mA,
V
E
= 0.5 V
Single Channel
Dual Channel
I
EL
I
EH
V
EH
V
EL
Low Level Enable Current
High Level Enable Current
High Level Enable Voltage
Low Level Enable Voltage
V
CC
= 5.5 V, V
E
= 0.5 V
V
CC
= 5.5 V, V
E
= 2.0 V
V
CC
= 5.5 V, I
F
= 10 mA
V
CC
= 5.5 V, I
F
= 10 mA
(3)
2.0
0.8
Single Channel
Dual Channel
V
CC
= 5.5 V,
I
F
= 10 mA
V
E
= 0.5 V
6
10
8
14
-0.7
-0.5
10
15
13
21
-1.6
-1.6
mA
mA
V
V
mA
mA
Input Forward Voltage
Input Reverse Breakdown
Voltage
Input Capacitance
Input Diode Temperature
Coefficient
I
F
= 10 mA
T
A
= 25°C
I
R
= 10 µA
V
F
= 0, f = 1 MHz
I
F
= 10 mA
5.0
60
-1.4
1.4
1.8
1.75
V
pF
mV/°C
V
Parameter
Test Conditions
Min.
Typ.*
Max.
Unit
Switching Characteristics
(T
A
= -40°C to +85°C, V
CC
= 5 V, I
F
= 7.5 mA unless otherwise specified)
Symbol
T
PLH
AC Characteristics
Propagation Delay
Time to Output HIGH
Level
Propagation Delay
Time to Output LOW
Level
Output Rise Time
(10% to 90%)
Output Rise Time
(90% to 10%)
Enable Propagation
Delay Time to Output
HIGH Level
Enable Propagation
Delay Time to Output
LOW Level
Common Mode
Transient Immunity
(at Output HIGH Level)
Test Conditions
R
L
= 350
Ω
,
C
L
= 15 pF
(4)
(Fig. 14)
T
A
= 25°C
(5)
R
L
= 350
Ω
, C
L
= 15 pF (Fig. 14)
R
L
= 350
Ω,
C
L
= 15 pF (Fig. 14)
R
L
= 350
Ω,
C
L
= 15 pF
(6)
(Fig. 14)
R
L
= 350
Ω,
C
L
= 15 pF
(7)
(Fig. 14)
I
F
= 7.5 mA, V
EH
= 3.5 V, R
L
= 350
Ω,
C
L
= 15 pF
(8)
(Fig. 15)
I
F
= 7.5 mA, V
EH
= 3.5 V, R
L
= 350
Ω,
C
L
= 15 pF
(9)
(Fig. 15)
T
A
= 25°C, |V
CM
| = 50 V 6N137M, HCPL2630M
(Peak), I
F
= 0 mA,
HCPL2601M,
V
OH
(Min.) = 2.0 V,
HCPL2631M
R
L
= 350
Ω
(10)
(Fig. 16)
|V
CM
| = 400 V
HCPL2611M
R
L
= 350
Ω,
I
F
= 7.5 mA, 6N137M, HCPL2630M
V
OL
(Max.) = 0.8 V,
HCPL2601M,
T
A
= 25°C
(11)
(Fig. 16)
HCPL2631M
|V
CM
| = 400 V
HCPL2611M
T
A
= 25°C
Min.
20
Typ.*
40
Max. Unit
75
100
ns
T
PHL
25
40
75
100
ns
|T
PHL
–T
PLH
| Pulse Width Distortion
t
r
t
f
t
ELH
1
30
10
15
35
ns
ns
ns
ns
t
EHL
15
ns
|CM
H
|
10,000
5000
10,000
V/µs
10,000
5000
10,000
15,000
10,000
10,000
15,000
V/µs
|CM
L
|
Common Mode
Transient Immunity
(at Output LOW Level)
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
www.fairchildsemi.com
4
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Electrical Characteristics
(Continued)
Transfer Characteristics
(T
A
= -40 to +85°C unless otherwise specified)
Symbol
I
OH
V
OL
I
FT
DC Characteristics
HIGH Level Output Current
LOW Level Output Current
Input Threshold Current
Test Conditions
V
CC
= 5.5 V, V
O
= 5.5 V,
I
F
= 250 µA, V
E
= 2.0 V
(2)
V
CC
= 5.5 V, I
F
= 5 mA, V
E
= 2.0 V,
I
CL
= 13 mA
(2)
V
CC
= 5.5 V, V
O
= 0.6 V, V
E
= 2.0 V,
I
OL
= 13 mA
Min.
Typ.*
Max.
100
Unit
µA
V
mA
0.4
3
0.6
5
Isolation Characteristics
(T
A
= -40°C to +85°C unless otherwise specified.)
Symbol
I
I-O
Characteristics
Input-Output Insulation
Leakage Current
Withstand Insulation Test
Voltage
Resistance (Input to Output)
Capacitance (Input to Output)
Test Conditions
Relative humidity = 45%,
T
A
= 25°C, t = 5 s,
V
I-O
= 3000 VDC
(12)
RH < 50%, T
A
= 25°C,
I
I-O
≤
10 µA, t = 1 min.
(12)
V
I-O
= 500 V
(12)
f = 1 MHz
(12)
Min.
Typ.*
Max.
1.0*
Unit
µA
V
ISO
R
I-O
C
I-O
5000
10
11
1
V
RMS
Ω
pF
*All Typicals at V
CC
= 5 V, T
A
= 25°C
Notes:
1. The V
CC
supply to each optoisolator must be bypassed by a 0.1 µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package V
CC
and GND pins of each device.
2. Each channel.
3. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
4. t
PLH
– Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
5. t
PHL
– Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. t
r
– Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. t
f
– Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. t
ELH
– Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
9. t
EHL
– Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
10. CM
H
– The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
HIGH state (i.e., V
OUT
> 2.0 V). Measured in volts per microsecond (V/µs).
11. CM
L
– The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
LOW output state (i.e., V
OUT
< 0.8 V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
www.fairchildsemi.com
5
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