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5962-9318714H4A

Description
Standard SRAM, 128KX32, 35ns, CMOS, PGA-66
Categorystorage    storage   
File Size259KB,11 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric View All

5962-9318714H4A Overview

Standard SRAM, 128KX32, 35ns, CMOS, PGA-66

5962-9318714H4A Parametric

Parameter NameAttribute value
Parts packaging codePGA
package instructionPGA, PGA66,11X11
Contacts66
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Is SamacsysN
Maximum access time35 ns
I/O typeCOMMON
JESD-30 codeS-XPGA-P66
JESD-609 codee0
length27.3 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width32
Number of functions1
Number of terminals66
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX32
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codePGA
Encapsulate equivalent codePGA66,11X11
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Filter levelMIL-PRF-38534 Class H
Maximum seat height4.95 mm
Maximum standby current0.005 A
Minimum standby current2 V
Maximum slew rate0.52 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width27.3 mm
Base Number Matches1
SRAM
Austin Semiconductor, Inc.
128K x 32 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-95595: -Q
• SMD 5962-93187: -P or -PN
• MIL-STD-883
AS8S128K32
PIN ASSIGNMENT
(Top View)
68 Lead CQFP (Q)
FEATURES
• Access times of 15, 17, 20, 25, 35, and 45 ns
• Built in decoupling caps for low noise operation
• Organized as 128K x32; User configured as
256Kx16 or 512K x8
• Operation with single 5 volt supply
• Low power CMOS
• TTL Compatible Inputs and Outputs
• 2V Data Retention, Low power standby
66 Lead PGA- Pins 8, 21, 28, 39 are grounds (P)
OPTIONS
Timing
15ns
17ns
20ns
25ns
35ns
45ns
Package
Ceramic Quad Flatpack
Pin Grid Array -8 Series
Pin Grid Array -8 Series
MARKINGS
-15
-17
-20
-25
-35
-45
Q
P
PN
No. 702
No. 802
No. 802
66 Lead PGA- Pins 8, 21, 28, 39 are no connects (PN)
NOTE:
PN indicates a no connect on pins 8, 21, 28, 39
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8S128K32 is a 4 Mega-
bit CMOS SRAM Module organized as 128Kx32-bits and user
configurable to 256Kx16 or 512Kx8. The AS8S128K32 achieves
high speed access, low power consumption and high reliability
by employing advanced CMOS memory technology.
The military temperature grade product is suited for mili-
tary applications.
The AS8S128K32 is offered in a ceramic quad flatpack mod-
ule per SMD-5962-95595 with a maximum height of 0.140 inches.
This module makes use of a low profile, mutlichip module de-
sign.
This device is also offered in a 1.075 inch square ceramic
pin grid array per SMD 5692-93187, which has a maximum height
of 0.195 inches. This package is also a low profile, multi-chip
module design reducing height requirements to a minimum.
CE4
WE4
128K x 8
CE3
WE3
M2
128K x 8
M3
I/O 24 - I/O 31
128K x 8
CE2
WE2
M1
I/O 16 - I/O 23
CE1
WE1
OE
A0 - 16
128K x 8
M0
I/O 8 - I/O 23
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS8S128K32
Rev. 3.5 7/00
I/O 0 - I/O 7
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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