K4S161622D-TI/E
CMOS SDRAM
1M x 16 SDRAM
512K x 16bit x 2 Banks
Synchronous DRAM
LVTTL
Industrial/ExtendedTemperature
Revision 1.2
Jan 2003
Samsung Electronics reserves the right to change products or specification without notice.
Rev 1.2 Jan '03
K4S161622D-TI/E
Revision History
Revision 1.0 (June 1999)
• Define Industrial Temperature spec of K4S161622D
CMOS SDRAM
Revision 1.1 (June 2001)
• Add Industrial Temperature Specification.
Revision 1.2 (Jan 2003)
• Changed VDD condition of High speed (over 166MHz) from 3.135V~ 3.6V to 3.0V ~ 3.0V.
Rev 1.2 Jan '03
K4S161622D-TI/E
512K x 16Bit x 2 Banks Synchronous DRAM
FEATURES
•
•
•
•
3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle (2K/32ms)
Extended temperature range : -25°C to +85°C
Industrial temperature range : -40°C to +85°C
CMOS SDRAM
GENERAL DESCRIPTION
The K4S161622D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
•
•
•
•
•
•
•
ORDERING INFORMATION
Part NO.
K4S161622D-TI/E50
K4S161622D-TI/E55
K4S161622D-TI/E60
K4S161622D-TI/E70
K4S161622D-TI/E80
K4S161622D-TI/E10
MAX Freq.
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
LVTTL
50
TSOP(II)
Interface Package
FUNCTIONAL BLOCK DIAGRAM
K4S161622D-TI* : Industrial, Normal
K4S161622D-TE* : Extended, Normal
I/O Control
LWE
LDQM
Data Input Register
Bank Select
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
512K x 16
Row Buffer
DQi
Address Register
CLK
ADD
512K x 16
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
Programming Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev 1.2 Jan '03
K4S161622D-TI/E
PIN CONFIGURATION
(TOP VIEW)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
CMOS SDRAM
50PIN TSOP (II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System Clock
Chip Select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
10
, column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
CKE
Clock Enable
A
0
~ A
10
/AP
BA
RAS
CAS
WE
L(U)DQM
DQ
0
~
15
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection/
Reserved for Future Use
Rev 1.2 Jan '03
K4S161622D-TI/E
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, Extended T
A
= -25 to +85°C , Industrial T
A
= -40 to +85°C)
Parameter
Supply voltage
Input logic high votlage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note
Note :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
:
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2
2
2
3
Max
4
4
4
5
Unit
pF
pF
pF
pF
Clock
RAS, CAS, WE, CS, CKE, L(U)DQM
Address
DQ
0
~ DQ
15
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between V
DD
and V
SS
Decoupling Capacitance between V
DDQ
and V
SSQ
Symbol
C
DC1
C
DC2
Value
0.1 + 0.01
0.1 + 0.01
Unit
uF
uF
Note :
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
Rev 1.2 Jan '03
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