CY7C1360C-166BGI datasheet, PDF

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CY7C1360C-166BGI: DescriptionCache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119; Categorystorage storage; File Size526KB，31 Pages; ManufacturerCypress Semiconductor

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CY7C1360C-166BGI Overview

Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

CY7C1360C-166BGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Is Samacsys	N
Maximum access time	3.5 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum standby current	0.04 A
Minimum standby current	3.14 V
Maximum slew rate	0.18 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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CY7C1360C

CY7C1362C

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Features

•

Supports bus operation up to 250 MHz

Available speed grades are 250, 200, and 166 MHz

Registered inputs and outputs for pipelined operation

3.3V core power supply (V

)

2.5V/3.3V I/O operation (V

DDQ

)

Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

Provide high-performance 3-1-1-1 access rate

User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

Separate processor and controller address strobes

Synchronous self-timed writes

Asynchronous output enable

Single Cycle Chip Deselect

Functional Description

[1]

The CY7C1360C/CY7C1362C SRAM integrates 256K x 36

and 512K x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE

), depth-expansion Chip

Enables (CE

and CE

3[2]

), Burst Control inputs (ADSC, ADSP,

and ADV), Write Enables (BW

, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the Byte Write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1360C/CY7C1362C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

Logic Block Diagram – CY7C1362C (512K x 18)

A0, A1, A

MODE

ADV

CLK

ADDRESS

A[1:0]

BURST Q1

COUNTER AND

LOGIC

CLR

ADSC

ADSP

DQP

WRITE REGISTER

DQP

WRITE DRIVER

MEMORY

ARRAY

BWE

CE2

CE3

ENABLE

DQP

WRITE REGISTER

DQP

WRITE DRIVER

SENSE

AMPS

OUTPUT

REGISTERS

OUTPUT

BUFFERS

DQs

DQP

PIPELINED

ENABLE

INPUT

REGISTERS

SLEEP

CONTROL

Notes:

1. For best-practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

2. CE

is for A version of TQFP (3 Chip Enable option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05540 Rev. *H

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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