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54FCT373CTQGB

Description
Bus Transceiver, 1-Func, 8-Bit, CMOS, PDSO20
Categorylogic    logic   
File Size90KB,7 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Environmental Compliance
Download Datasheet Parametric View All

54FCT373CTQGB Overview

Bus Transceiver, 1-Func, 8-Bit, CMOS, PDSO20

54FCT373CTQGB Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid4035307165
package instructionSSOP, SSOP20,.25
Reach Compliance Codecompliant
JESD-30 codeR-PDSO-G20
JESD-609 codee3
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS TRANSCEIVER
MaximumI(ol)0.048 A
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP20,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply5 V
Prop。Delay @ Nom-Sup5.1 ns
Certification statusNot Qualified
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
IDT54/74FCT373T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL
TRANSPARENT LATCH
IDT54/74FCT373T/AT/CT
FEATURES:
Std., A, and C grades
Low input and output leakage
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
– Industrial: SOIC, SSOP, QSOP
– Military: CERDIP, LCC
DESCRIPTION:
The FCT373Tis an octal transparent latch built using an advanced dual
metal CMOS technology. These octal latches have 3-state outputs and are
intended for bus oriented applications. The flip-flops appear transparent to
the data when Latch Enable (LE) is high. When LE is low, the data that meets
the set-up time is latched. Data appears on the bus when the Output Enable
(OE) is low. When
OE
is high, the bus output is in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
JUNE 2006
DSC-5496/5
© 2002 Integrated Device Technology, Inc.
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