SY89296U
2.5V/3.3V 1.5GHz Precision
LVPECL Programmable Delay
with Fine Tune Control
Precision Edge
®
General Description
The SY89296U is a programmable delay line that delays
the input signal using a digital control signal. The delay
can vary from 3.2ns to 14.8ns in 10ps increments. Further,
the delay may be varied continuously in about 40ps range
by setting the voltage at the FTUNE pin. In addition, the
input signal is LVPECL, uses either a 2.5V ±5% or 3.3V
±10% power supply, and is guaranteed over the full
industrial temperature range (–40°C to +85°C).
The delay varies in discrete steps based on a control word.
The control word is 10-bits long and controls the delay in
10ps increments. The eleventh bit is D[10] and is used to
simultaneously cascade the SY89296U for a larger delay
range. In addition, the input pins IN and /IN default to an
equivalent low state when left floating. Further, for
maximum flexibility, the control register interface accepts
CMOS or TTL level signals.
For applications that do not require an analog delay input,
see the SY89295U. The SY89295U and SY89296U are
part of Micrel’s high-speed, Precision Edge
®
product line.
Data sheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Precision Edge
®
Features
•
Precision LVPECL programmable delay time
•
Guaranteed AC performance over temperature and
voltage:
−
>1.5GHz
f
MAX
−
<160ps
rise/fall times
•
Low jitter design:
−
<10ps
PP
total jitter
−
<2ps
RMS
cycle-to-cycle jitter
−
<1ps
RMS
random jitter
•
Programmable delay range: 3.2ns to 14.8ns in 10ps
increments
•
Increased monotonicity over the MC100EP195
• ±10ps
INL
•
VBB output reference voltage
•
Parallel inputs accept LVPECL or CMOS/LVTTL
•
40ps/V fine tune range
•
Low voltage operation: 2.5V
±5%
and 3.3V
±10%
•
Industrial
−40°C
to
+85°C
temperature range
•
Available in 32-pin (5mm
×
5mm) MLF
®
package or
32-pin TQFP package
Applications
•
Clock de-skewing
•
Timing adjustments
•
Aperture centering
Precision Edge is a registered trademark of Micrel, Inc
MLF and
MicroLeadFrame
are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
November 2011
M9999-112211
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89296U
Pin Description
Pin Number
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
Pin Name
Pin Function
CMOS, ECL, or TTL Control Bits: These control signals adjust the delay from IN to Q. See
“AC Electrical Characteristics” for delay values. In addition, see “Interface Applications”
section which illustrates the proper interfacing techniques for different logic standards.
D[9:0] contains pull-downs and defaults LOW when left floating. D0 (LSB), and D9 (MSB).
See “Typical Operating Characteristics” for delay information.
CMOS, ECL, or TTL Control Bit: This bit is used to cascade devices for an extended
delay range. In addition, it drives CASCADE and /CASCADE. Further, D[10] contains a
pull-down and defaults LOW when left floating.
LVPECL/ECL Signal Input: Input signal to be delayed. IN contains a 75kΩ pull-down and
will default to a logic LOW if left floating.
Reference Voltage Output: When using a single-ended input signal source to IN or /IN,
connect the unused input of the differential pair to this pin. This pin can also be used to
rebias AC-coupled inputs to IN and /IN. When used, de-couple to V
CC
using a 0.01µF
capacitor, otherwise leave floating if not used. Maximum sink/source is ±0.5mA.
Reference Voltage Output: Connect this pin to V
CF
when D[9:0], and D[10] is ECL.
Logic Standard
LVPECL
CMOS
TTL
8
9, 24, 28
10
11
VCF
GND,
(2)
Exposed Pad
LEN
SETMIN
V
CF
Connects to:
V
EF(1)
No Connect
1.5V Source
D[9:0]
3
4, 5
D10
IN, /IN
6
7
VBB
(1)
VEF
Reference Voltage Input: The voltage driven on VCF sets the logic transition threshold for
D[9:0], and D[10].
Negative Supply: For MLF® package, exposed pad must be connected to a ground plane
that is the same potential as the ground pin.
ECL Control Input: When HIGH latches the D[9:0] and D[10] bits. When LOW, the D[9:0]
and D[10] latches are transparent.
ECL Control Input: When HIGH, D[9:0] registers are reset. When LOW, the delay is set by
SETMAX or D[9:0] and D[10]. SETMIN contains a pull-down and defaults LOW when left
floating.
ECL Control Input: When SETMAX is set HIGH and SETMIN is set LOW, D[9:0] =
1111111111. When SETMAX is LOW, the delay is set by SETMIN or D[9:0] and D[10].
SETMAX contains a pull-down and defaults LOW when left floating.
Positive Power Supply: Bypass with 0.1µF and 0.01µF low ESR capacitors.
LVPECL Differential Output: The outputs are used when cascading two or more
SY89296U to extend the delay range.
LVPECL Single-Ended Control Input: When LOW, Q is delayed from IN. When HIGH, Q is
a differential LOW. /EN contains a pull-down and defaults LOW when left floating.
LVPECL Differential Output: Q is a delayed version of IN, Always terminates the output
with 50Ω to VCC – 2V. See “Output Interface Applications” section.
Voltage Control Input: By varying the voltage, the delay is fine tuned, see the graph,
“Propagation Delay vs. FTUNE Voltage.” Leave pin floating if not used.
12
13, 18, 19, 22
14, 15
16
20, 21
17
Notes
:
1.
2.
SETMAX
VCC
/Cascade,
Cascade
/EN
/Q, Q
FTUNE
Single-ended operation is only functional at 3.3V.
MLF® package only.
November 2011
3
M9999-112211
hbwhelp@micrel.com
or (408) 955-1690
京公网安备 11010802033920号
EEWORLD
